Patents by Inventor Bart Sorgeloos
Bart Sorgeloos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10181464Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.Type: GrantFiled: June 16, 2017Date of Patent: January 15, 2019Assignee: SOFICS BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
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Patent number: 9881914Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.Type: GrantFiled: May 5, 2017Date of Patent: January 30, 2018Assignee: SOFICS BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
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Publication number: 20180006016Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.Type: ApplicationFiled: June 16, 2017Publication date: January 4, 2018Applicant: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
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Publication number: 20170243864Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.Type: ApplicationFiled: May 5, 2017Publication date: August 24, 2017Applicant: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
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Patent number: 9685431Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.Type: GrantFiled: September 29, 2014Date of Patent: June 20, 2017Assignee: SOFICS BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
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Patent number: 9653453Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.Type: GrantFiled: May 23, 2016Date of Patent: May 16, 2017Assignee: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
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Publication number: 20160268250Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.Type: ApplicationFiled: May 23, 2016Publication date: September 15, 2016Applicant: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
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Patent number: 9349716Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.Type: GrantFiled: February 6, 2013Date of Patent: May 24, 2016Assignee: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
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Publication number: 20150091056Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Applicant: SOFICS BVBAInventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
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Patent number: 8830641Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.Type: GrantFiled: March 4, 2013Date of Patent: September 9, 2014Assignee: Sofics BVBAInventors: Johan Van Der Borght, Sven Van Wijmeersch, Benjamin Van Camp, Bart Sorgeloos
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Publication number: 20130229736Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.Type: ApplicationFiled: March 4, 2013Publication date: September 5, 2013Applicant: SOFICS BVBAInventors: Johan Van Der Borght, Sven Van Wijmeersch, Benjamin Van Camp, Bart Sorgeloos
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Patent number: 8283698Abstract: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.Type: GrantFiled: April 15, 2010Date of Patent: October 9, 2012Assignee: Sofics BVBAInventors: Bart Sorgeloos, Benjamin Van Camp
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Patent number: 7986502Abstract: An ESD protection circuit including an SCR having at least a PNP transistor and at least a NPN transistor such that said PNP transistor is coupled to an anode and the NPN transistor is coupled to a cathode. The circuit also includes a first resistor coupled between the anode and the base of the pnp transistor and a second resistor coupled between the cathode and the base of the npn transistor. A parasitic distributed bipolar transistor is formed between said first and second transistor to control triggering of the SCR.Type: GrantFiled: July 9, 2009Date of Patent: July 26, 2011Assignee: Sofics BVBAInventor: Bart Sorgeloos
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Publication number: 20100264457Abstract: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.Type: ApplicationFiled: April 15, 2010Publication date: October 21, 2010Inventors: Bart Sorgeloos, Benjamin Van Camp
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Publication number: 20100008002Abstract: An ESD protection circuit including an SCR having at least a PNP transistor and at least a NPN transistor such that said PNP transistor is coupled to an anode and the NPN transistor is coupled to a cathode. The circuit also includes a first resistor coupled between the anode and the base of the pnp transistor and a second resistor coupled between the cathode and the base of the npn transistor. A parasitic distributed bipolar transistor is formed between said first and second transistor to control triggering of the SCR.Type: ApplicationFiled: July 9, 2009Publication date: January 14, 2010Inventor: Bart Sorgeloos
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Publication number: 20090195951Abstract: An ESD protection circuit having a triggering device, an ESD device and a circuit device coupled between the triggering device and the circuit device such that the circuit device conducts current only in one direction between the ESD device and the triggering device so the ESD device is in an active state for duration longer than time constant of the triggering device.Type: ApplicationFiled: February 5, 2009Publication date: August 6, 2009Inventors: Bart Sorgeloos, Pieter Vanysacker
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Publication number: 20080285187Abstract: The present invention provides a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises a substrate of first conductivity type; a MOS component of second conductivity type formed on a first well on the substrate, and coupled to a pad; an isolating well/region having the second conductivity type being formed between the first well and the substrate to separate the first well and the substrate. Additionally, the circuit comprises an ESD clamp coupled to the isolated well/region. Under normal power operation, the ESD clamp is open. During a CDM ESD event, the CDM charges accumulated in the substrate and the MOS component are removed by the ESD clamp to prevent damage to the IC.Type: ApplicationFiled: May 17, 2007Publication date: November 20, 2008Inventors: Benjamin Van Camp, Bart Sorgeloos
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Publication number: 20080218920Abstract: An apparatus having an inter-domain electrostatic discharge (ESD) protection circuit for protection of an integrated circuit (IC) with multiple power domains. The protection circuit in response to an ESD event provides an ESD protection between different power domains. Specifically, the protection circuit comprises at least one clamp coupled to one power domain, which conducts current during an ESD event to provide extra current in the interface line between the two different power domains. This extra current also in turn increases the voltage over the impedance element on the interface line, thus improving the design margins for the ESD protection and providing a better ESD protection capability for IC products.Type: ApplicationFiled: March 6, 2008Publication date: September 11, 2008Applicants: SARNOFF CORPORATION, SARNOFF EUROPE BVBAInventors: Pieter Vanysacker, Olivier Marichal, Bart Sorgeloos, Benjamin Van Camp, Bart Keppens, Johan Van der Borght
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Publication number: 20080002321Abstract: The present invention provides an ESD protection circuit for a ESD clamp such as an SCR in the protection of an integrated circuit. In one embodiment of the invention, the SCR having at least one interspersed high-doped first region formed within a first lightly doped region and at least one interspersed high-doped second region formed within a second lightly doped region. The circuit further comprising at least one guardring connected to at least one trigger tap of the SCR to collect the ESD current to provide for a fast and easier triggering of the SCR.Type: ApplicationFiled: June 27, 2007Publication date: January 3, 2008Inventors: Bart Sorgeloos, Bart Keppens, Benjamin Van Camp