Patents by Inventor Bart Van Velzen
Bart Van Velzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250258213Abstract: Example embodiments relate to die crack detection systems. An example die crack detection system includes a semiconductor device and a measuring unit. The semiconductor device includes a semiconductor body in or on which at least one component is integrated and that comprises a conductive region. The semiconductor device also includes an electrically insulating layer arranged on the conductive region. Additionally, the semiconductor device includes a first conductive trace arranged on the electrically insulating layer. Further, the semiconductor device includes a first contact that is electrically connected to the first conductive trace. In addition, the semiconductor device includes a second contact that is electrically connected to the conductive region. The first conductive trace, the electrically insulating layer, and the conductive region form a capacitor. The first contact is arranged at an end of the first conductive trace. The first conductive trace includes a fifth contact.Type: ApplicationFiled: February 7, 2025Publication date: August 14, 2025Inventors: Mariano Ercoli, Stephan Maroldt, Bart Van Velzen
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Publication number: 20250062220Abstract: Example embodiments relate to vertically stacked capacitors. One capacitor assembly includes a vertical stacking of a first capacitor and a second capacitor on a substrate. The first capacitor includes a first terminal and a second terminal. The second terminal is formed by a first conductive layer that includes stress relief openings. The second capacitor includes a first terminal and a second terminal. The second terminal of the first capacitor lies below the first terminal of the first capacitor. The second terminal of the second capacitor lies below the first terminal of the second capacitor. The second capacitor lies below the first capacitor. The capacitor assembly further includes a ground layer. The second terminal of the second capacitor is electrically connected to the ground layer and to the first conductive layer. The ground layer includes stress relief openings. The ground layer is configured to be electrically grounded during operation.Type: ApplicationFiled: August 15, 2024Publication date: February 20, 2025Inventors: Daniel Maassen, Bart Van Velzen
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Patent number: 9385116Abstract: An electrostatic discharge (ESD) protection device on a semiconductor substrate and a method for making the same. The device has an active region. The active region includes a gate. The active region also includes a source including a silicide portion having a source contact. The active region further includes a drain including a silicide portion having a drain contact. The source and drain each extend away from the gate along a device axis. The drain contact is laterally offset with respect to the source contact along a direction orthogonal to the device axis whereby current flow between the source contact and the drain contact has a lateral component. The device further comprises a non-silicide region located laterally between the drain contact and the source contact.Type: GrantFiled: April 22, 2015Date of Patent: July 5, 2016Assignee: NXP B.V.Inventors: Dolphin Abessolo Bidzo, Bart van Velzen
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Publication number: 20150311194Abstract: An electrostatic discharge (ESD) protection device on a semiconductor substrate and a method for making the same. The device has an active region. The active region includes a gate. The active region also includes a source including a silicide portion having a source contact. The active region further includes a drain including a silicide portion having a drain contact. The source and drain each extend away from the gate along a device axis. The drain contact is laterally offset with respect to the source contact along a direction orthogonal to the device axis whereby current flow between the source contact and the drain contact has a lateral component. The device further comprises a non-silicide region located laterally between the drain contact and the source contact.Type: ApplicationFiled: April 22, 2015Publication date: October 29, 2015Inventors: Dolphin Abessolo Bidzo, Bart van Velzen
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Patent number: 8872359Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.Type: GrantFiled: June 24, 2010Date of Patent: October 28, 2014Assignee: NXP, B.V.Inventors: Bart Van Velzen, Hans Van Zadelhoff, Greja Johanna Adriana Maria Verheijden
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Publication number: 20120091561Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.Type: ApplicationFiled: June 24, 2010Publication date: April 19, 2012Applicant: NXP B.V.Inventors: Bart Van Velzen, Hans Van Zadelhoff, Greja Verheijden
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Patent number: 8058952Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.Type: GrantFiled: December 18, 2006Date of Patent: November 15, 2011Assignee: NXP B.V.Inventors: Jozef T. M. Van Beek, Bart Van Velzen
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Publication number: 20090121808Abstract: The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.Type: ApplicationFiled: December 18, 2006Publication date: May 14, 2009Applicant: NXP B.V.Inventors: Jozef T.M. Van Beek, Bart Van Velzen