Abstract: An apparatus for reproducing a digitally encoded signal from a disk medium, comprises a transducer which transduces the digitally encoded signal. A memory is coupled to the transducer for storing the digitally encoded signal. A decoder is responsive to the digitally encoded signal for decoding a picture therefrom. A controller for the memory, wherein a first operational mode the controller controls the memory to read the stored digitally encoded signal from the memory responsive to a first sequence and in a second operational mode the controller controls the memory to read the stored digitally encoded signal from the memory in a second sequence.

Abstract: Jitter of an overlay display with respect to the primary display of a television receiver is avoided by assuring that the vertical and horizontal blanking signal components are sufficiently time spaced by preventing the number of clock pulses occurring between the horizontal and vertical components of the blanking signal from going below a selected number. The number of clock pulses between the negative going transition of the vertical blanking signal and the positive going transition of the first horizontal blanking signal is tracked and when the number of pulses fails to exceed a reference value the number of pulses is changed to effectively shift the transitions with respect to one another.

Abstract: A video display has a first format display ratio. A mapping circuit maps an adjustable picture display are on the video display. A signal processor generates first and second video signals from input video signals having one of different format display ratios. A switching circuit selectively couples video signal sources as the input video signals. The signal processor can manipulate data from the input video signals by selective interpolation and cropping. A synchronizing circuit synchronizes the first and second signal processors with the mapping circuit. A selecting circuit selects as an output video signal between one of the first and second processed video signals and a combination of the first and second processed video signals. A control circuit controls the mapping circuit, the first and second signal processors and the selecting circuit to adjust in format display ratio and image aspect ratio each picture represented in the output video signal.

Abstract: First and second field type detectors for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory and an asynchronous multiple line memory. The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit, which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type.

Abstract: A wide screen television apparatus comprises a video display having a first format display ratio of width to height, for example approximately 16.times.9. A first video signal defines a first picture. A second video signal defines a second picture in a second format display ratio of width to height smaller than the first format display ratio, for example approximately 4.times.3. A video signal processor asymmetrically compresses the second picture, for example 4:1 horizontally and 3:1 vertically. A video memory stores lines of video of the asymmetrically compressed picture. Another video signal processor combines portions of lines of video in the first video signal with the stored lines of video of the asymmetrically compressed picture for simultaneous display of the first and second pictures. The asymmetrically compressed second picture is displayed without aspect ratio distortion. The second picture can form an inset within the first picture.

Abstract: A field synchronization system for asynchronous video signals, comprises a video display synchronized with a first video signal having a first line rate component and a first field rate component. A second video signal having a second line rate component is first stored in a field memory, having synchronous write and read ports. The second video signal is thereafter speeded up in a multiple line memory having asynchronous write and read ports and independently resettable write and read pointers. The second video signal may be subsampled, written and read into and out of the field memory respectively and written into the multiple line memory, all synchronously with the second line rate component. The second video signal is read out of the multiple line memory synchronously with the first line rate component. The write pointer is reset by a circuit which samples the first field rate component with the second line rate component.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Abstract: A picture-in-picture system including panning and scrolling capability moves an inset image about a display in synchronism with the vertical field rate in order to provide smooth movement from one display position to another.

Abstract: Apparatus for controlling the time constant of a signal includes an up/down counter for counting pulses of a clock signal. The count value is utilized as output signal. The output signal is compared with the input signal to provide a first control signal determinative of whether the counter counts up or down. The output signal is compared with the input signal offset by a constant value to provide a signal which is ORed with the first control signal, and the ORed signal is utilized to enable/disable the counter. Applying a constant offset value to the input signal to be compared precludes the system from alternately counting up and down by one unit value during intervals of relatively constant amplitude input signals.

Abstract: A PIP system stores data indicative of the location of the center point of an inset picture with respect to a display screen center point in a memory area of a first size. The inset image data is read out of the memory area beginning with the data stored in a memory location known as the "read address". When a ZOOM-IN or ZOOM-OUT command is received, data representing a new video image of a different size is stored for display in an unused memory area of a different size, a new inset center point is computed, and a new read address is computed, so that the displayed centers of the new inset area of a different size, and the old inset area are substantially the same.

Abstract: In a video signal processing system apparatus for differentiating between video field types includes circuitry for measuring an interval between a vertical signal component and a predetermined transition of a horizontal signal component. Measured values from successive fields are compared to provide a signal related to the respective field type, e.g., odd/even.

Abstract: A picture-in-a-picture television receiver displays a compound image which includes a compressed image derived from an auxiliary signal inset in a full-size image derived from a main signal. The auxiliary composite video signal is sampled synchronous with a system clock signal that is burst locked to the main signal. The sampled data signal is separated into luminance and color information component signals, which are subsampled and stored in a field memory synchronous with the system clock signal. The clock signal phase used for horizontal subsampling is determined at the start of each line to compensate for skew errors in the auxiliary signal. The luminance samples retrieved from the memory are applied to clock transfer circuitry which resynchronizes the samples to a phase shifted version of the system clock signal to compensate for skew errors in the main signal. The phase shifted clock signal is synchronized to the horizontal scanning signals used to display the compound image.

Abstract: A video processing system includes apparatus for panning and magnifying portions of a source image stored in memory. Viewer control circuitry generates center coordinates of the portion of the image to be displayed and also a magnification factor. Further circuitry, responsive to the center coordinates and the magnification factor, generates starting addresses for reading the appropriate portion of the source image from memory. The system monitors the relative values of the center coordinates and the magnification factor to preclude blanking intervals of the source image from being displayed.

Abstract: A picture-in-a-picture television receiver includes a memory for holding samples representing a vertically and horizontally compressed image. The memory is divided into three parts, a main portion which holds one field of the compressed image and first and second crossover buffers, each of which hold one line of the compressed signal. Both upper and lower field types may be derived from each field of the auxiliary signal used to produce the compressed image. Sample values are stored into the memory such that an upper field of the compressed image is stored when an upper field of the main image is displayed and a lower field is stored when a lower field is displayed. When the address used to read samples from the memory overtakes the address used to write samples into the memory, the type of field derived from the auxiliary signal is switched and one line of samples is directed to one of the crossover buffers.

Abstract: A digital D.C. control system includes a multiplexer, a digital-to-analog converter, a capacitor, offset generating circuitry and clamping circuitry. A digital signal to be D.C. controlled and a digital brightness control signal are alternatively coupled by the multiplexer to the input of the digital-to-analog converter. The output from the digital-to-analog converter is coupled to a system output terminal via the capacitor. When the signal is applied to the digital-to-analog converter a fixed D.C. offset is applied to the interconnection of the converter and capacitor. During preselected intervals the D.C. control value is coupled to the digital-to-analog converter concurrently with the system output terminal being clamped to a fixed reference and the D.C. offset circuitry being disabled. This combination of apparatus permits controlling the D.C. level of a digitally processed signal without affecting the dynamic range of the digital signal.