Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

Abstract: A method for sorting data in an array processor. Each of a first tier of processing elements in the array processor receives data inputs from a load streaming unit. Each of the first tier processing elements compares input data portions received from the load streaming unit, wherein the input data portions are stored for processing in respective queues. The first tier processing elements select one of the input data portions to be an output data portion based on the comparison, and in response to the selection, remove a corresponding queue entry and request next input data from the load streaming unit. Each of the first tier processing elements further provides the output data portion as an input data portion to a second tier processing element that generates output data based on a comparison of output data received from at least two first tier processing elements.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspension. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: An array processor includes a managing element having a load streaming unit coupled to multiple processing elements. The load streaming unit provides input data portions to each of a first subset of the processing elements and also receives output data from each of a second subset of the processing elements based on a comparatively sorted combination of the input data portions provided to the first subset of processing elements. Furthermore, each of processing elements is configurable by the managing element to compare input data portions received from either the load streaming unit or two or more of the other processing elements, wherein the input data portions are stored for processing in respective queues. Each processing unit is further configurable to select an input data portion to be output data based on the comparison, and in response to selecting the input data portion, remove a queue entry corresponding to the selected input data portion.

Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Abstract: An array processor includes a managing element having a load streaming unit coupled to multiple processing elements. The load streaming unit provides input data portions to each of a first subset of processing elements and receives output data from each of a second subset of the processing elements based on a comparatively sorted combination of the input data portions. Each processing element is configurable by the managing element to compare input data portions received from the load streaming unit or two or more of the other processing elements. Each processing unit can further select an input data portion to be output data based on the comparison, and in response to selecting the input data portion, remove a queue entry corresponding to the selected input data portion. Each processing element can provide the selected output data portion to the managing element or as an input to one of the processing elements.

Abstract: A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Multiple clients may attempt to utilize a coprocessor engine within a coprocessor simultaneously. However, each engine may accomplish the particular function for which it is designed for one client at a time. Therefore, to transition from performing coprocessor engine operations between clients, the coprocessor engine may be suspended from performing operations for a first client so that it may begin performing operations for a second client. Prior to such transition, the coprocessor engine saves metadata about its operation state at the time of the suspend. At a subsequent time, when operations for the first client are to resume, the operating state of the coprocessor engine is determined utilizing the metadata and operations for the first client resume.

Abstract: Operation of a multi-slice computer processor that includes a plurality of execution slices. Operation of such a computer processor includes: matching one or more sub strings of a data string to one or more substrings of a data set; determining that a particular substring of the one or more substrings of the data string corresponds to a highest priority value among one or more priority values mapped to one or more encodings for the one or more substrings of the data string; and encoding, in dependence upon the particular substring of the data string corresponding to the highest priority value, the data string into an encoding that encodes the particular substring of the one or more substrings of the data string.

Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Abstract: A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.

Abstract: Techniques for creating a dynamic Huffman table in hardware are provided. In one aspect, a method for encoding data includes the steps of: implementing dynamic Huffman tables in hardware representing a plurality of Huffman tree shapes precomputed from a sample data set, wherein the Huffman tree shapes are represented in the dynamic Huffman tables by code length values; upon receipt of input data, writing symbols and their counts from the input data to the dynamic Huffman tables; calculating a score for each of the dynamic Huffman tables with the symbols and counts from the input data, wherein the score is based on the code length values of the precomputed Huffman tree shapes and the counts from the input data and selecting a given one of the dynamic Huffman tables having a lowest score for encoding the input data. A process for implementing the present techniques in SRAM is also provided.

Abstract: A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.