Patents by Inventor Bartholomew Liao
Bartholomew Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220093479Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: JCET Semiconductor (Shaoxing) Co., Ltd.Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
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Patent number: 11227809Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: GrantFiled: March 13, 2017Date of Patent: January 18, 2022Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
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Patent number: 10109587Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: August 2, 2016Date of Patent: October 23, 2018Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9865554Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: GrantFiled: November 30, 2015Date of Patent: January 9, 2018Assignee: STATS ChipPAC Ptc. Ltd.Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao Chung Foh, Zigmund Ramirez Camacho
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Publication number: 20170186660Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Applicant: STATS ChipPAC Pte. Ltd.Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
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Patent number: 9679769Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.Type: GrantFiled: June 30, 2016Date of Patent: June 13, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
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Patent number: 9659897Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.Type: GrantFiled: May 27, 2016Date of Patent: May 23, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
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Patent number: 9627338Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: GrantFiled: February 21, 2014Date of Patent: April 18, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
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Patent number: 9502267Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.Type: GrantFiled: June 26, 2014Date of Patent: November 22, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
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Patent number: 9412624Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.Type: GrantFiled: June 26, 2014Date of Patent: August 9, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
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Patent number: 9406642Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.Type: GrantFiled: March 9, 2015Date of Patent: August 2, 2016Assignee: STATS ChipPAC Ltd.Inventors: HeeJo Chi, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Zigmund Ramirez Camacho, Dao Nguyen Phu Cuong
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Patent number: 9406531Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.Type: GrantFiled: March 28, 2014Date of Patent: August 2, 2016Assignee: STATS ChipPAC Pte. Ltd.Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
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Patent number: 9355983Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.Type: GrantFiled: June 27, 2014Date of Patent: May 31, 2016Assignee: STATS ChipPAC Ltd.Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
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Patent number: 9331003Abstract: An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.Type: GrantFiled: March 28, 2014Date of Patent: May 3, 2016Assignee: STATS ChipPac Ltd.Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
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Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
Patent number: 9330994Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer.Type: GrantFiled: March 28, 2014Date of Patent: May 3, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Bartholomew Liao, Sheila Marie L. Alvarez, HeeJo Chi, Kelvin Dao -
Publication number: 20160099222Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: ApplicationFiled: November 30, 2015Publication date: April 7, 2016Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao Chung Foh, Zigmund Ramirez Camacho
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Patent number: 9202793Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.Type: GrantFiled: December 26, 2013Date of Patent: December 1, 2015Assignee: STATS ChipPAC Ltd.Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao, Zigmund Ramirez Camacho
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Semiconductor Device and Method of Forming RDL and Vertical Interconnect by Laser Direct Structuring
Publication number: 20150279778Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Applicant: STATS ChipPAC, Ltd.Inventors: Zigmund R. Camacho, Bartholomew Liao, Sheila Marie L. Alvarez, HeeJo Chi, Kelvin Dao -
Publication number: 20150179602Abstract: An integrated circuit packaging system and method of manufacture thereof including: an integrated circuit die having a contact pad; a redistribution layer on the contact pad, the redistribution layer having a chip contact, a trace, and a bump pad, the redistribution layer having a curved top surface and sidewalls which are planar; an upper passivation layer on the sidewalls of the redistribution layer with the area above the bump pad of the redistribution layer exposed from the upper passivation layer; and an external interconnect attached over the bump pad.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Zigmund Ramirez Camacho, Bartholomew Liao, Sheila Marie L. Alvarez, Kelvin Dao
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Publication number: 20140252641Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: ApplicationFiled: February 21, 2014Publication date: September 11, 2014Applicant: STATS ChipPAC, Ltd.Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao