Abstract: A structure includes a cavity in a semiconductor substrate; a field effect transistor positioned over the cavity; an opening in the semiconductor substrate extending to the cavity; and a layer of insulating material filling the opening and forming an insulating material window to the cavity.

Abstract: Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

Abstract: Disclosed is a structure (e.g., a lab-on-chip structure) including a substrate, an insulator layer on the substrate, and at least one optical ring resonator. Each ring resonator includes cladding material on the insulator layer and, embedded within the cladding material, a first waveguide core with an input and an output, and second waveguide core(s) (e.g., ring waveguide core(s)) positioned laterally adjacent to the first waveguide core. A reservoir is below the ring resonator within the insulator layer and substrate such that surfaces of the waveguide cores are exposed within the reservoir. During a sensing operation, the waveguide core surfaces contact with fluid within the reservoir and a light signal at the output of the first waveguide core is monitored (e.g., by a sensing circuit, which in some embodiments is also coupled to a reference optical ring resonator) and used, for example, for spectrum-based target identification and, optionally, characterization.

Abstract: Disclosed is a structure (e.g., a lab-on-chip structure) including a substrate, an insulator layer on the substrate, and at least one optical ring resonator. Each ring resonator includes cladding material on the insulator layer and, embedded within the cladding material, a first waveguide core with an input and an output, and second waveguide core(s) (e.g., ring waveguide core(s)) positioned laterally adjacent to the first waveguide core. A reservoir is below the ring resonator within the insulator layer and substrate such that surfaces of the waveguide cores are exposed within the reservoir. During a sensing operation, the waveguide core surfaces contact with fluid within the reservoir and a light signal at the output of the first waveguide core is monitored (e.g., by a sensing circuit, which in some embodiments is also coupled to a reference optical ring resonator) and used, for example, for spectrum-based target identification and, optionally, characterization.

Abstract: A structure includes a first layer having a recess. The structure further includes an intermediate layer contacting the first layer and a contact-free biosensor aligned above the recess. The portion of the intermediate layer that is positioned along the recess separates the contact-free biosensor from the recess.

Abstract: Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A waveguide core includes a longitudinal axis, a first section, and a second section spaced from the first section along the longitudinal axis. An active layer includes a portion positioned along the longitudinal axis between the first section and the second section of the waveguide core. The active layer contains a material configured to have a first state with a first refractive index in response to an applied stimulus and a second state with a second refractive index different from the first refractive index.

Abstract: Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A waveguide core includes a longitudinal axis, a first section, and a second section spaced from the first section along the longitudinal axis. An active layer includes a portion positioned along the longitudinal axis between the first section and the second section of the waveguide core. The active layer contains a material configured to have a first state with a first refractive index in response to an applied stimulus and a second state with a second refractive index different from the first refractive index.

Abstract: Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.

Abstract: Structures including a buffer layer and methods of forming a structure including a buffer layer. A layer stack is formed on a semiconductor substrate. The layer stack includes a buffer layer and a charge-trapping layer. The buffer layer is composed of a III-V compound semiconductor material, and the charge-trapping layer is positioned between the semiconductor substrate and the buffer layer.

Abstract: Disclosed is a quantum-confined Stark effect (QCSE) modulator. In the modulator, a first doped semiconductor region has a first type conductivity, is at the bottom of a trench in a dielectric layer and is immediately adjacent to a semiconductor layer. An MQW region is in the trench on the first doped semiconductor region and at least upper segments of sidewalls of the MQW region are angled away from adjacent sidewalls of the trench such that there are spaces between the MQW region and the dielectric layer. Dielectric spacers fill the spaces. A second doped semiconductor region has a second type conductivity, is on top of the MQW region and optionally extends laterally onto the tops of the dielectric spacers. The spacers prevent shorting of the doped semiconductor regions. Also disclosed are embodiments of a photonics structure including the modulator and of methods for forming the modulator and the photonics structure.

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

Abstract: Structures and fabrication methods for a vertical-transport field-effect transistor. A plurality of pillars comprised of a semiconductor material are formed. First and second gate structures are located along a length of the pillars. The second gate structure is vertically spaced along the length of the pillars relative to the first gate structure. The first and second gate structures are each associated with a channel defined in the pillars.