Abstract: The disclosure describes a control memory for addressing inlet and outlet switching stages of a three stage digital switch. The control memory comprises two identical random access memories (RAM's) each having an address storage capacity equal to half the number of simplex connections which can be made through either stage of the switch. The arrangement described allows a large saving in the number of memory bits necessary to address the inlet and outlet switching stages and enables fast access of the control memory for the purpose of establishing or terminating connections.

Abstract: A method for the supervision of clock signals in a digital data system in which data is clocked progressively by clock signals through a number of registers includes supervisory flip flops associated with each register with a clock supervision bit progressively clocked through the flip flops which together from a supervision chain. The absence of one or more of the clock signals prevents the clock supervision bit from propagating to the end of the chain. By monitoring said clock supervision bit after propagation through the supervision chain it can be determined whether clock signals are supplied correctly to all registers.