Abstract: Approaches for performing in line wafer testing are provided. An approach includes a method that includes generating a radio frequency (RF) test signal, and applying the RF test signal to a device under test (DUT) in a wafer using a buckling beam probe set with a predefined pitch. The method also includes detecting an output RF signal from the DUT in response to the applying the RF test signal to the DUT, and sensing at least one frequency component of the detected output RF signal.

Abstract: A test device including cobra probes and a method of manufacturing is disclosed. The test device includes a conductive upper plate having an upper guide hole and a conductive lower plate having a lower guide hole. The test device also includes a conductive cobra probe disposed between the upper guide hole of the upper plate and the lower guide hole of the lower plate. A dielectric material insulates the cobra probe from the upper plate and the lower plate.

Abstract: A test device including cobra probes and a method of manufacturing is disclosed. The test device includes a conductive upper plate having an upper guide hole and a conductive lower plate having a lower guide hole. The test device also includes a conductive cobra probe disposed between the upper guide hole of the upper plate and the lower guide hole of the lower plate. A dielectric material insulates the cobra probe from the upper plate and the lower plate.

Abstract: A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector (216) and a glitch detector (208) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.

Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.

Abstract: An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.