Patents by Inventor Barton G. Shaler

Barton G. Shaler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6625440
    Abstract: A drum memory controller for controlling random access write and sequential read operations of a drum memory in a communications system. Such drum memory controller (220) may comprise a drum memory (224) having a predetermined number of rows and rings forming a plurality of memory locations arranged in a sequential time order; a random access write address generator (222) which generates write addresses using a respective time tag of incoming data for writing data into memory locations of the drum memory (224) in a random access time order; and a sequential reader (226) which generates read addresses at a constant rate for reading out data stored in the memory locations of the drum memory (224) across each row and then sequencing up in rows in a sequential time order.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 23, 2003
    Assignee: TRW Inc.
    Inventors: Barton G. Shaler, Stephane Mailleau
  • Patent number: 6557062
    Abstract: A system and method for controlling Radio Frequency (RF) devices. A serial RF control bus (106) provides a half-duplex serial communication interconnect path between a bus master (108) and one or more bus slaves (110). The bus master is coupled to a processor (102), and each bus slave is coupled to an RF device (104) that operates without a free-running clock. The processor controls the RF devices by sending and receiving messages over the RF control bus. The bus master and bus slaves format these messages for transmission across the RF control bus. The RF control bus includes a bi-directional data line (120), a first clock line (124), and a second clock line (122). The first clock line is asserted by the bus master when transmitting serial data to and receiving serial data from the RF slaves via the data line. The second clock line is asserted by the RF slaves when transmitting serial data to the bus master via the data line.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 29, 2003
    Assignee: TRW Inc.
    Inventors: Barton G. Shaler, Steve Caras
  • Patent number: 6320750
    Abstract: A line replaceable module (LRM) configured with a plurality of mini-modules, each of which have relatively higher contact densities than currently available LRMs with the same form factor, for example, a Standard Electrical Module-Size E (SEM-E) form factor. The mini-modules are significantly less expensive than an entire module allowing such mini-modules to be disposable, eliminating relatively costly fault diagnostics and repair. Each mini-module includes a printed circuit board which includes a rigid primary portion, a rigid secondary portion and flexible portion interconnecting the primary and secondary portions. The rigid secondary portion may be configured to provide dual-sided interconnection to a backplane data bus. Use of the dual-sided rigid secondary portion provides for generous spacing for contact densities much higher than known contact densities for LRMs with the same form factor. The rigid primary portion carries the components forming the LRM.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: November 20, 2001
    Assignee: TRW Inc.
    Inventors: Barton G. Shaler, Donald A. Porter, Milton F. Damerow
  • Publication number: 20010015888
    Abstract: A line replaceable module (LRM) configured with a plurality of mini-modules, each of which have relatively higher contact densities than currently available LRMs with the same form factor, for example, a Standard Electrical Module-Size E (SEM-E) form factor. The mini-modules are significantly less expensive than an entire module allowing such mini-modules to be disposable, eliminating relatively costly fault diagnostics and repair. Each mini-module includes a printed circuit board which includes a rigid primary portion, a rigid secondary portion and flexible portion interconnecting the primary and secondary portions. The rigid secondary portion may be configured to provide dual-sided interconnection to a backplane data bus. Use of the dual-sided rigid secondary portion provides for generous spacing for contact densities much higher than known contact densities for LRMs with the same form factor. The rigid primary portion carries the components forming the LRM.
    Type: Application
    Filed: November 24, 1998
    Publication date: August 23, 2001
    Inventors: BARTON G. SHALER, DONALD A. PORTER, MILTON F. DAMEROW