Patents by Inventor Barton J. Sano
Barton J. Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080228871Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.Type: ApplicationFiled: May 30, 2008Publication date: September 18, 2008Applicant: BROADCOM CORPORATIONInventor: Barton J. Sano
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Patent number: 7424561Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.Type: GrantFiled: March 13, 2007Date of Patent: September 9, 2008Assignee: Broadcom CorporationInventors: Barton J. Sano, Joseph B. Rowlands, Laurent R. Moll, Manu Gulati
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Publication number: 20080198867Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.Type: ApplicationFiled: April 25, 2008Publication date: August 21, 2008Applicant: Broadcom CorporationInventors: Laurent Moll, Barton J. Sano, Thomas Albert Petersen
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Patent number: 7394823Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.Type: GrantFiled: October 11, 2002Date of Patent: July 1, 2008Assignee: Broadcom CorporationInventor: Barton J. Sano
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Patent number: 7366092Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.Type: GrantFiled: October 14, 2003Date of Patent: April 29, 2008Assignee: Broadcom CorporationInventors: Laurent Moll, Barton J. Sano, Thomas Albert Petersen
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Patent number: 7227870Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.Type: GrantFiled: October 11, 2002Date of Patent: June 5, 2007Assignee: Broadcom CorporationInventors: Barton J. Sano, Laurent R. Moll, Manu Gulati
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Patent number: 7206879Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.Type: GrantFiled: October 11, 2002Date of Patent: April 17, 2007Assignee: Broadcom CorporationInventors: Barton J. Sano, Joseph B. Rowlands, Laurent R. Moll, Manu Gulati
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Patent number: 6941406Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.Type: GrantFiled: June 4, 2004Date of Patent: September 6, 2005Assignee: Broadcom CorporationInventors: Barton J. Sano, Joseph B. Rowlands, James B. Keller, Laurent R. Moll, Koray Oner, Manu Gulati
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Patent number: 6912602Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.Type: GrantFiled: October 11, 2002Date of Patent: June 28, 2005Assignee: Broadcom CorporationInventors: Barton J. Sano, Koray Oner, Laurent R. Moll, Manu Gulati
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Publication number: 20040221072Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.Type: ApplicationFiled: June 4, 2004Publication date: November 4, 2004Inventors: Barton J. Sano, Joseph B. Rowlands, James B. Keller, Laurent R. Moll, Koray Oner, Manu Gulati
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Patent number: 6748479Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.Type: GrantFiled: October 11, 2002Date of Patent: June 8, 2004Assignee: Broadcom CorporationInventors: Barton J. Sano, Joseph B. Rowlands, James B. Keller, Laurent R. Moll, Koray Oner, Manu Gulati
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Publication number: 20030105828Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.Type: ApplicationFiled: October 11, 2002Publication date: June 5, 2003Applicant: Broadcom Corp.Inventors: Barton J. Sano, Joseph B. Rowlands, Laurent R. Moll, Manu Gulati
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Publication number: 20030097416Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.Type: ApplicationFiled: October 11, 2002Publication date: May 22, 2003Applicant: Broadcom Corp.Inventors: Barton J. Sano, Joseph B. Rowlands, James B. Keller, Laurent R. Moll, Koray Oner, Manu Gulati
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Publication number: 20030097467Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.Type: ApplicationFiled: October 11, 2002Publication date: May 22, 2003Applicant: Broadcom Corp.Inventor: Barton J. Sano
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Publication number: 20030097498Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.Type: ApplicationFiled: October 11, 2002Publication date: May 22, 2003Applicant: Broadcom Corp.Inventors: Barton J. Sano, Koray Oner, Laurent R. Moll, Manu Gulati
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Publication number: 20030095559Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.Type: ApplicationFiled: October 11, 2002Publication date: May 22, 2003Applicant: Broadcom Corp.Inventors: Barton J. Sano, Laurent R. Moll, Manu Gulati