Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

Abstract: In general, the cache structure overcomes the deficiency of wasted tag space and reduces associativity. The method provides for storing a single tag along with a pointer to the actual data which is stored in a separate array which includes several lines. Each data block may have a variable length and occupy several lines. These lines are linked together to form a linked list. An invalidation mechanism allows invalidation of lines of the same data block, increasing data efficiency.

Abstract: Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting decoded instructions, detecting segment beginning and end conditions and storing instruction segments is conserved by disabling those circuits that perform these functions. An access filter may maintain a running count of the number of times instructions are read from an instruction cache and may enable the segment construction and storage circuits if the running count meets or exceeds a predetermined threshold.

Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.

Abstract: In general, the cache structure overcomes the deficiency of wasted tag space and reduces associativity. The method provides for storing a single tag along with a pointer to the actual data which is stored in a separate array which includes several lines. Each data block may have a variable length and occupy several lines. These lines are linked together to form a linked list. An invalidation mechanism allows invalidation of lines of the same data block, increasing data efficiency.