Patents by Inventor Baruch Yanovitch

Baruch Yanovitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BANDWIDTH EFFICIENT INSTRUCTION-DRIVEN MULTIPLICATION ENGINE
    Publication number: 20140074901
    Abstract: Multiplication engines and multiplication methods are provided for a digital processor.
    Type: Application
    Filed: October 16, 2013
    Publication date: March 13, 2014
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Andreas D. Olofsson, Baruch Yanovitch
  • Bandwidth efficient instruction-driven multiplication engine
    Patent number: 8589469
    Abstract: Multiplication engines and multiplication methods are provided for a digital processor.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: November 19, 2013
    Assignee: Analog Devices Technology
    Inventors: Andreas D. Olofsson, Baruch Yanovitch
  • Multi-format multiplier unit
    Patent number: 8275822
    Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: September 25, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Andreas D. Olofsson, Baruch Yanovitch
  • Bandwidth efficient instruction-driven multiplication engine
    Publication number: 20080222226
    Abstract: Multiplication engines and multiplication methods are provided for a digital processor.
    Type: Application
    Filed: January 10, 2008
    Publication date: September 11, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Andreas D. Olofsson, Baruch Yanovitch
  • Multi-format multiplier unit
    Publication number: 20080195685
    Abstract: Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from input operands in a first multiplier mode; a second multiplier to generate equally weighted partial products from input operands in a second multiplier mode; a multiplexer to select the unequally weighted partial products in the first multiplier mode and to select the equally weighted partial products in the second multiplier mode; and a carry save adder array configured to combine the selected partial products in the first multiplier mode and in the second multiplier mode.
    Type: Application
    Filed: January 10, 2008
    Publication date: August 14, 2008
    Applicant: Analog Devices, Inc.
    Inventors: Andreas D. Olofsson, Baruch Yanovitch