Patents by Inventor Basab Banerjee

Basab Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9419101
    Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jianwei Peng, Hong Yu, Zhao Lun, Tao Han, Hsien-Ching Lo, Basab Banerjee, Wen Zhi Gao, Byoung-Gi Min
  • Patent number: 6995437
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery
  • Patent number: 6780708
    Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: August 24, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hiroyuki Kinoshita, Yu Sun, Basab Banerjee, Christopher M. Foster, John R. Behnke, Cyrus Tabery