Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parametrized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge.

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge.

Abstract: A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.

Abstract: An apparatus and method for forming at least a portion of an electronic device include a High Vacuum-Chemical Vapor Deposition (UHV-CVD) system and a Low Pressure-Chemical Vapor Deposition (LPCVD) system using a common reactor. The invention overcomes the problem, of silicon containing wafers being dipped in HF acid prior to CVD processing, and the problem of surface passivation between processes in multiple CVD reactors.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.