Patents by Inventor Basavaraj Pawate

Basavaraj Pawate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5719344
    Abstract: A Karaoke system scoring method and system (10) is provided based on detecting, for example, frame energy (19 or 19') of the Karaoke singer and the frame energy of the original artist (29 or 29'). The frame energy is quantized (41 and 43) and compared (45) and based on the comparison a score (37) is generated and displayed (15).
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: February 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Basavaraj Pawate
  • Patent number: 5528549
    Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 18, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: George R. Doddington, Basavaraj Pawate, Shivaling Mahant-Shetti, Derek Smith
  • Patent number: 5528550
    Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 18, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Basavaraj Pawate, George Doddington, Shivaling S. Mahant-Shetti, Derek Smith
  • Patent number: 5500828
    Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 19, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: George D. Doddington, Basavaraj Pawate, Shivaling Mahant-Shetti, Derek Smith
  • Patent number: 5390139
    Abstract: A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: February 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Derek Smith, Shivaling Mahant-Shetti, Basavaraj Pawate, George R. Doddington, Warren L. Bean