Abstract: Disclosed are systems and methods for transmission and reception of data bits. A plurality of data bits are received. FEC-based encoded data bits are generated in accordance with a zipper code framework incorporating component non-binary codes. The zipper code framework includes a buffer having a virtual buffer and a real buffer. Codewords associated with the FEC-based encoded data bits are stored in rows of the real buffer. A given codeword in a given row of the real buffer is mapped to different rows of the virtual buffer in a quasi-diagonal interleaving manner.

Abstract: Forward Error Correction decoding is executed by acquiring a stream of real data symbols from a communication medium, the stream of real data symbols being arranged in a real matrix. Virtual data symbols are generated and arranged in a virtual matrix by applying an interleaver map onto the real matrix. Codewords formed by a main matrix formed by the real matrix and the virtual matrix are iteratively decoded, an iteration of the decoding comprising identifying a set of consecutive received rows of the main matrix, accessing a set of pre-determined reference codewords and in response to determining that a given codeword of the set of consecutive received rows does not match any pre-determined reference codewords, executing a GRAND algorithm on the given codeword, the GRAND algorithm generating a substitute codeword for the given codeword. A system comprising a processor and a memory executes the Forward Error Correction decoding.

Abstract: Forward Error Correction decoding is executed by acquiring a stream of real data symbols from a communication medium, the stream of real data symbols being arranged in a real matrix. Virtual data symbols are generated and arranged in a virtual matrix by applying an interleaver map onto the real matrix. Codewords formed by a main matrix formed by the real matrix and the virtual matrix are iteratively decoded, an iteration of the decoding comprising identifying a set of consecutive received rows of the main matrix, accessing a set of pre-determined reference codewords and in response to determining that a given codeword of the set of consecutive received rows does not match any pre-determined reference codewords, executing a GRAND algorithm on the given codeword, the GRAND algorithm generating a substitute codeword for the given codeword. A system comprising a processor and a memory executes the Forward Error Correction decoding.

Abstract: The disclosed systems and methods for transmission and reception comprising: i) receiving a plurality of data bits; ii) generating FEC-based encoded data bits in accordance with a zipper code framework incorporating component non-binary codes, wherein the zipper code framework including a buffer having a virtual buffer and a real buffer; iii) storing codewords associated with the FEC-based encoded bits in rows of the real buffer; iv) mapping a given codeword in a given row of the real buffer to different rows of the virtual buffer; v) receiving an analog signal transmitted by a transmitter; vi) processing the received analog signal and generating received forward error correction (FEC)-based encoded bits in accordance with a zipper code framework that incorporates component non-binary codes; and vii) decoding the received FEC-based encoded bits in accordance with a non-binary decoding technique and generating information bits.

Abstract: There is provided methods and processors for executing Forward Error Correction (FEC) coding. The method includes acquiring a stream of real data symbols from a communication medium. The stream of real data symbols being arranged in a real matrix. The method includes generating virtual data symbols being arranged in a virtual matrix. The generating includes applying an interleaver map onto the matrix such that (i) at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of (ii) real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1. The method includes decoding codewords formed by the virtual matrix and the matrix.

Abstract: There is provided methods and processors for executing Forward Error Correction (FEC) coding. The method includes acquiring a stream of real data symbols from a communication medium. The stream of real data symbols being arranged in a real matrix. The method includes generating virtual data symbols being arranged in a virtual matrix. The generating includes applying an interleaver map onto the matrix such that (i) at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of (ii) real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1. The method includes decoding codewords formed by the virtual matrix and the matrix.