Abstract: A pin configuration logic circuit (120) has a pin function register (130) which defines a selected pin function, such as chip enable, write enable, and output enable, to be provided as a chip select signal. The logic circuit (120) allows an arbitrary pipeline length by causing the chip select signal to obey only the timing of the active cycle. For a two-deep access pipeline, the logic circuit (120) marks whether a first or a second cycle owns the pin. The pin configuration logic circuit (120) uses the timing associated with the selected pin function to provide the chip select signal during the first cycle if the attributes of the cycle, such as an access to a region programmed in the pin function register, are met. During the second cycle, the pin configuration logic circuit (120) further obeys the timing associated with the selected pin function if the attributes of that cycle are also met.