Abstract: The disclosure relates to method and system for determining network congestion level. The method includes determining a round trip time (RTT) for each high priority and for each low priority packet transaction in the precision time protocol (PTP) protocol. The high priority and the low priority packet transactions are conducted between a master device and a slave device within a pre-defined time window. The method further includes determining an average high priority RTT and an average low priority RTT based on the RTT for each high priority packet transaction and for each low priority packet transaction respectively, computing an average delta RTT based on a difference between the average high priority RTT and the average low priority RTT, and determining an instantaneous network congestion level based on the average delta RTT and a reference delta RTT for a number of pre-defined time windows since a start of the slave device.

Abstract: The disclosure relates to method and system for determining network congestion level. The method includes determining a round trip time (RTT) for each high priority and for each low priority packet transaction in the precision time protocol (PTP) protocol. The high priority and the low priority packet transactions are conducted between a master device and a slave device within a pre-defined time window. The method further includes determining an average high priority RTT and an average low priority RTT based on the RTT for each high priority packet transaction and for each low priority packet transaction respectively, computing an average delta RTT based on a difference between the average high priority RTT and the average low priority RTT, and determining an instantaneous network congestion level based on the average delta RTT and a reference delta RTT for a number of pre-defined time windows since a start of the slave device.

Abstract: A method and system for clock synchronization in an electronic device based on time based control is disclosed. The method includes comparing a current value of a cumulative phase difference between a signal generated by a device clock and a reference signal, with a reset threshold. The method further includes generating a control value, when the current value is greater than the reset threshold. Generating the control value includes computing a startup correction value based on a time lapsed after reset of the device clock, a dynamic correction value based on an accuracy factor, a clock constant, and a comparison of a current phase difference between with a high error threshold, and computing the control value based on the startup correction value, the dynamic correction value, and the current value of the cumulative phase difference. The method includes adjusting a frequency of the device clock based on the control value.

Abstract: A method and system for clock synchronization in an electronic device based on time based control is disclosed. The method includes comparing a current value of a cumulative phase difference between a signal generated by a device clock and a reference signal, with a reset threshold. The method further includes generating a control value, when the current value is greater than the reset threshold. Generating the control value includes computing a startup correction value based on a time lapsed after reset of the device clock, a dynamic correction value based on an accuracy factor, a clock constant, and a comparison of a current phase difference between with a high error threshold, and computing the control value based on the startup correction value, the dynamic correction value, and the current value of the cumulative phase difference. The method includes adjusting a frequency of the device clock based on the control value.

Abstract: The invention concerns a method of electrodeposition onto a semiconductor. The surface lattice structure of the semiconductor is first disturbed, by an ion beam or otherwise, and then the semiconductor is immersed in an electroplating solution. When the semiconductor is irradiated with light of sufficiently short wavelength to generate free charge carriers therein, ions from the solution are deposited on the semiconductor surface. Metal ions are deposited by this technique only on the disturbed regions of the semiconductor surface, providing an excellent selective deposition process. Multiple layers may be deposited, and even different metals on different regions of the semiconductor surface. The method is particularly suited to the production of solid slate devices such as, for example, gallium arsenide field effect transistors.