Abstract: An automated simulation method for determining the enhanced generation-recombination rate due to trap-to-band tunnelling in a semiconductor device using the Dirac coulombic tunelling integral and to a simulator for carrying out the method are disclosed. The method and simulator are, for example, particularly useful in the modelling of characteristics such as leakage current in polysilicon TFTs, which leakage current can, for example, seriously degrade pixel voltage in active matrix display devices.

Abstract: A device and automated method of calculating bulk states information and interface states information of a thin film transistor from a current-voltage measurement and a capacitance-voltage measurement comprising the steps of: calculating the flat band voltage from the input capacitance-voltage measurement; applying a general expression of Gauss's Law and the calculated flat band voltage to a capacitance voltage relationship which define capacitance so as to calculate a relationship between gate surface potential and gate/source voltage; applying Gauss's Law to the calculated relationship between gate surface potential and gate/source voltage to thereby calculate and ouput the interface states; calculating conductance/gate voltage data from the current-voltage measurement using the calculated flat band voltage; conducting an initialisation process using the calculated conductance/gate voltage data and the calculated relationship between gate surface potential and gate/source voltage, said initialisat

Abstract: The present invention provides, in a TFT, a gate electrode and a channel domain that are plurally divided in the channel-length direction, a low-concentration domain that is formed between the divided channel domains, and a low-concentration drain domain that adjoins a second channel domain located closest to a drain domain side among the divided channel domains. Therefore, even if the impurity concentration is relatively high in the low-concentration domain located between the divided channel domains and a low-concentration drain domain, an abnormal increase of drain current in the saturated region can be prevented, and a TFT with a high drain current level can be obtained. Thus, the present invention provides a TFT and its manufacturing method where abnormal increase of drain current in the saturated region can be prevented and the drain current level in the saturated region is sufficiently high.

Abstract: A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the gate electrode is split, the active layer has a doped region located between the source and the drain and aligned with the split in the gate electrode, and the gate electrode is aligned with the drain so as not to overlap the drain. The transistor may be formed using a method comprising the steps of: providing a semiconductor layer in which the source and drain are to be formed; forming a gate insulating layer on the semiconductor layer; forming a split gate electrode on the gate insulating layer; and using the split gate electrode as a mask in the doping of a portion of the semiconductor layer between the source and the drain of the final transistor.

Abstract: A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the active layer has at least one recombination center which is located between the source and the drain and which extends from the substrate side through the active layer for less than the full depth thereof. The transistor can be fabricated by depositing the recombination centers on the substrate prior to depositing the active layer or by other methods such as diffusing material from the substrate side into the active layer.

Abstract: A semiconductor transistor comprising a substrate (10) having an active layer (14) formed thereon, a source (32) and a drain (30,38) formed in the active layer, a gate insulating layer (16) formed on the active layer and a gate electrode (34) formed on the insulating layer, wherein the gate electrode is split, the active layer has a doped region (36) located between the source and the drain and aligned with the split in the gate electrode, and the gate electrode is aligned with the drain so as not to overlap the drain. The transistor may be formed using a method comprising the steps of: providing a semiconductor layer (14) in which the source (32) and drain (30, 38) are to be formed; forming a gate insulating layer (16) on the semiconductor layer; forming a split gate electrode (34) on the gate insulating layer, and using the split gate electrode as a mask in the doping of a portion (36) of the semiconductor layer between the source and the drain of the final transistor.

Abstract: The present invention provides, in a TFT, a gate electrode and a channel domain that are plurally divided in the channel-length direction, a low-concentration domain that is formed between the divided channel domains, and a low-concentration drain domain that adjoins a second channel domain located closest to a drain domain side among the divided channel domains. Therefore, even if the impurity concentration is relatively high in the low-concentration domain located between the divided channel domains and a low-concentration drain domain, an abnormal increase of drain current in the saturated region can be prevented, and a TFT with a high drain current level can be obtained. Thus, the present invention provides a TFT and its manufacturing method where abnormal increase of drain current in the saturated region can be prevented and the drain current level in the saturated region is sufficiently high.