Patents by Inventor Basil Milton

Basil Milton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079396
    Abstract: A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Applicant: KULICKE AND SOFFA INDUSTRIES, INC.
    Inventors: Basil Milton, David Jeffery Li, Wei Qin
  • Patent number: 12183711
    Abstract: A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: December 31, 2024
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, David Jeffery Li, Wei Qin
  • Publication number: 20240363583
    Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, Romeo Olida, Jonathan Geller, Tomer Levinson
  • Patent number: 12057431
    Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: August 6, 2024
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, Romeo Olida, Jonathan Geller, Tomer Levinson
  • Publication number: 20230335532
    Abstract: A method of determining a height value of a wire loop on a wire bonding machine is provided. The method includes the steps of: (a) imaging at least a portion of a wire loop using an imaging system on a wire bonding machine to detect a path of the portion of the wire loop; (b) moving a wire bonding tool towards a first contact portion of the wire loop in the path; (c) detecting when a portion of a conductive wire engaged with the wire bonding tool contacts the first contact portion of the wire loop; and (d) determining a height value of the wire loop at the first contact portion based on a position of the wire bonding tool when the portion of the conductive wire contacts the first contact portion of the wire loop.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 19, 2023
    Inventors: Basil Milton, Wei Qin, Zhijie Wang, Vladimir Pribula, Pavel Shusharin
  • Publication number: 20230325552
    Abstract: A method of determining suitability of a wire bonding tool for a wire bonding application is provided. The method includes the steps of: (a) providing specifications for a wire bonding tool; and (b) determining if the wire bonding tool is acceptable for a wire bonding application using (i) a software tool and (ii) the specifications provided in step (a).
    Type: Application
    Filed: March 2, 2023
    Publication date: October 12, 2023
    Inventors: Basil Milton, Wei Qin
  • Publication number: 20230325578
    Abstract: A method of determining an effect of electronic component placement accuracy on wire loops in a semiconductor package is provided. The method includes the steps of: (a) providing package data for a semiconductor package, the semiconductor package including an electronic component; (b) simulating placement of the electronic component in a plurality of positions with respect to a substrate in the semiconductor package; and (c) determining, using a software tool, an effect of each of the plurality of positions of the electronic component on a plurality of wire loops included in the semiconductor package.
    Type: Application
    Filed: March 14, 2023
    Publication date: October 12, 2023
    Inventors: Basil Milton, Wei Qin
  • Publication number: 20230260960
    Abstract: A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).
    Type: Application
    Filed: February 14, 2023
    Publication date: August 17, 2023
    Inventors: Basil Milton, David Jeffery Li, Wei Qin
  • Publication number: 20220199570
    Abstract: A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Inventors: Basil Milton, Romeo Olida, Jonathan Geller, Tomer Levinson
  • Patent number: 11289448
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 29, 2022
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, Wei Qin
  • Publication number: 20200251444
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Basil Milton, Wei Qin
  • Patent number: 10672735
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 2, 2020
    Assignee: Kulicke and Soffa Industries, Inc.
    Inventors: Basil Milton, Wei Qin
  • Publication number: 20190259730
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Basil Milton, Wei Qin
  • Patent number: 10325878
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 18, 2019
    Assignee: KULICKE AND SOFFA INDUSTRIES, INC.
    Inventors: Basil Milton, Wei Qin
  • Publication number: 20180005980
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Application
    Filed: June 15, 2017
    Publication date: January 4, 2018
    Inventors: Basil Milton, Wei Qin