Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node.

Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.

Abstract: An apparatus for interpolating between a first signal and a second signal is provided. The apparatus includes a first plurality of interpolation cells configured to generate a first interpolation signal at a first node. At least one of the first plurality of interpolation cells is configured to supply, based on a first number of bits of a control word, at least one of the first signal and the second signal to the first node. The apparatus further includes a second plurality of interpolation cells configured to generate a second interpolation signal at a second node. At least one of the second plurality of interpolation cells is configured to supply, based on a second number of bits of the control word, at least one of the first signal and the second signal to the second node.

Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.