Abstract: A method and apparatus for reading a value provided by an electronic device and using that value to derive and set a timing parameter for a bus to which the electronic device is attached.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: A method and apparatus for reading a value provided by an electronic device and using that value to derive and set a timing parameter for a bus to which the electronic device is attached.

Abstract: In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.

Abstract: In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.

Abstract: A fault resilient circuit, having a ring counter, that boots a multi-device system, such as multi-processor computer system. A timer accepts start timer and system operational signals and produces a system fail signal. A ring counter accepts the system fail signal, and the ring counter produces a plurality of device control signals. With such an arrangement, when enabling all of the devices substantially simultaneously does not produce a working system, the boot circuit can for, example, enable all but one of the devices and determine if the system operates correctly with all but one of the devices enabled. If the system does not operate correctly with all but one of the devices enabled, a single device in the system can be enabled and it is determined if the system operates correctly with a single device enabled.

Abstract: In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

Abstract: An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combined PERR# signal.

Abstract: A method for setting host bus clock frequencies and processor core clock ratios in a multi-processor computer system. The method first determines original host bus frequency settings for each of the installed processors. The host bus is set to clock at the slowest of the frequency settings. Processor core clock ratios are then optimized for the new host bus frequency. The optimization process commences by determining the original processor core clock ratio settings for each processor. These ratio settings are individually optimized via an iterative process wherein the core clock ratios are incrementally increased and multiplied by the new host bus frequency. This process continues until the incremented core clock ratio yields a core clock frequency in excess of the maximum rating for the processor under test. The core clock ratio is then decremented and latched into the processor under test via a hard reset.

Abstract: The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.

Abstract: In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.