Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

Abstract: The present disclosure relates to a tray assembly. The tray assembly may include a die transport tray. The die transport tray may include an inner bottom surface for accommodating a plurality of dies. The tray assembly may further include a lid. The lid may include an inner top surface, wherein the inner top surface of the lid may face the inner bottom surface of the die transport tray when the lid is assembled over the die transport tray. The lid may further include a shock absorbing material on the inner top surface for contacting the plurality of dies, if present.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed.

Abstract: A transport carrier assembly for transporting integrated circuit dice may be formed comprising a rigid carrier frame and a compliant carrier insert attached within the rigid carrier frame. In one embodiment, the rigid carrier frame may conform to a standard, such that processing equipment may uniformly handle and transport the transport carrier assembly, and the compliant carrier insert may have differing configurations to house corresponding integrated circuit die configurations. In a further embodiment, the rigid carrier frame may comprise a substantially non-resilient material to provide structural integrity and the compliant carrier insert may comprise a substantially resilient material to protect the integrated circuit dice disposed therein during shipping and processing events.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.

Abstract: A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated adhesive on the carrier tape.

Abstract: A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated adhesive on the carrier tape.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.

Abstract: Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations.