Abstract: An embedded controller (EC) of an information handling system is configured to detect and respond to anomalous conditions in which a pre-boot or runtime error has occurred and EC-local storage resources are not sufficient to store EC telemetry data, by redirecting the EC telemetry data through an available communication channel, e.g., SBIOS MBOX packets or ACPI MMIO, to offload the data to EC-external storage such as an ESP partition or Cloud storage. In a pre-boot mode, SBIOS may invoke a UEFI storage driver to write out EC log data to EC-external storage, e.g., SSD/NVMe device or the Cloud. In a runtime mode, the EC may be flagged by an OS bugcheck handler, e.g., via eSPI MMIO path, to save the log data. In an OS-context mode, ACPI methods may notify a persistent driver, e.g., Common Platform Services (CPS) driver, to write out the log to the EC-external storage.

Abstract: Methods and systems for managing communications is disclosed. A host device and a management controller may communicate via memory mapped communications using shared memory. To improve the security of the memory mapped communications, access requests for shared memory may be monitored. Access controls for the shared memory may be put in place to reduce the likelihood of data being made unavailable before it is processed. The access controls may be lifted when the data stored in shared memory has been read by to complete the memory mapped communications.

Abstract: Methods and systems for managing communications is disclosed. A host device and a management controller may communicate via memory mapped communications using shared memory. To improve the security of the memory mapped communications, access requests for shared memory may be monitored. Access controls for the shared memory may be put in place to reduce the likelihood of data being made unavailable before it is processed. The access controls may be lifted when the data stored in shared memory has been read by to complete the memory mapped communications.

Abstract: In some embodiments, a power converter circuit includes a first power converter coupled between a direct-current (DC) node and a first pair of output nodes. The first power converter may be configured to provide a first power signal having a first phase to the first pair of output nodes. The power converter circuit may also include a second power converter coupled between the DC node and a second pair of output nodes. The second power converter may be configured to provide a second power signal having a second phase to the second pair of output nodes. The second phase and the first phase may differ by an odd multiple of ninety degrees.

Abstract: In some embodiments, a power converter circuit includes a first power converter coupled between a direct-current (DC) node and a first pair of output nodes. The first power converter may be configured to provide a first power signal having a first phase to the first pair of output nodes. The power converter circuit may also include a second power converter coupled between the DC node and a second pair of output nodes. The second power converter may be configured to provide a second power signal having a second phase to the second pair of output nodes. The second phase and the first phase may differ by an odd multiple of ninety degrees.