Abstract: A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage Vbias_substrate may be applied to the substrate.

Abstract: A method for preparing a microelectronic component includes cleaning of the surface of an exposed layer with a basis of a III-V material by a cyclic plasma treatment, each cycle comprising a purge phase and a plasma treatment phase. During the formation of the plasma, a bias voltage is applied to the substrate. The method further includes depositing, on the cleaned surface, a subsequent layer. The method provides an optimal cleaning of the exposed layer while minimising, and preferably avoiding degradation of the structure. The preparation method thus makes it possible to improve the quality of the interface between the layer with a basis of a III-V material and the subsequent layer. The electrical properties of the component are consequently improved.

Abstract: A method of forming nanowires, including the forming on a metal region of a layer having through openings, and the forming in the through openings of portions deposited in a chemical bath, forming all or part of the nanowires and extending from the metal region.

Abstract: A nanowire forming method, including the forming of a DNA origami having through openings, and the forming in the through openings of portions forming all or part of the nanowires.

Abstract: A method for producing, on a structure based on a material III-V, of a dielectric layer, the method comprising producing a first dielectric film by ALD by carrying out a plurality of first cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a first material and one injection in the reaction chamber of a water or ozone-based precursor; and producing, on the first dielectric film, a second dielectric film by plasma-enhanced ALD by carrying out a plurality of second cycles, each comprising at least: one injection in the reaction chamber of a precursor based on a second material and one injection in the reaction chamber of an oxygen or nitrogen based precursor.

Abstract: A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage Vbias_substrate may be applied to the substrate.

Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: The piezoelectric device includes a first electrode, a second electrode, piezoelectric elongate nano-objects in contact with the first electrode, and extending between the first electrode and the second electrode, a first layer of an electrically-insulating first material, the first layer surrounding a first longitudinal portion of each of the piezoelectric elongate nano-objects, a second layer of an electrically-insulating second material, the second layer surrounding a second longitudinal portion of each of the piezoelectric elongate nano-objects. The first layer is arranged between the first electrode and the second layer. The thickness of the first layer is strictly smaller than the thickness of the second layer. The first material has a Young's modulus strictly higher than the Young's modulus of the second material.

Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: The transistor (100) comprises a nanowire (101) at least partially forming a channel of the transistor (100), a source contact (102) arranged at a first longitudinal end (103) of the nanowire (101), a drain contact (104) arranged at a second longitudinal end (105) of the nanowire (101), and a gate (106) arranged on the nanowire (101) between the source contact (102) and the drain contact (104). Furthermore, a portion of the gate (106) covers, with the interposition of a dielectric material (107), a corresponding portion of the source contact (102) and/or of the drain contact (104) arranged along the nanowire (101) between its two longitudinal ends (103, 105).

Abstract: Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.

Abstract: Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.