Patents by Inventor Bastien Cousin

Bastien Cousin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for the radiation hardening of an electronic circuit by partitioning
    Patent number: 9270271
    Abstract: The method relates to a method for the radiation hardening of an electronic circuit by partitioning, said circuit including an odd number K of parallel branches connected to a same primary input I and each including a same series of N modules and N?1 nodes linking two consecutive modules, the K branches together forming a series of N?1 gates respectively consisting of parallel K nodes, and a primary arbiter forming a majority vote from the output signal of the K branches, the method being characterized in that it includes the following steps which are repeated for each one of the gates: determining a reliability of a subcircuit upstream from the gate consisting of the portions of the K branches located between the primary input and the gate, and the insertion of at least one arbiter at the gate forming a majority vote from the output signals of said portions of branches constituting the scanned subcircuit and outputting at least one majority signal to the respective inputs of an additional subcircuit formed b
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: February 23, 2016
    Assignee: Electricite De France
    Inventors: Bastien Cousin, Gilles Deleuze, Laurent Cretinon, Gutemberg Goncalves Dos Santos, Jr., Lirida Naviner
  • METHOD FOR THE RADIATION HARDENING OF AN ELECTRONIC CIRCUIT BY PARTITIONING
    Publication number: 20150295578
    Abstract: The method relates to a method for the radiation hardening of an electronic circuit by partitioning, said circuit including an odd number K of parallel branches connected to a same primary input I and each including a same series of N modules and N?1 nodes linking two consecutive modules, the K branches together forming a series of N?1 gates respectively consisting of parallel K nodes, and a primary arbiter forming a majority vote from the output signal of the K branches, the method being characterized in that it includes the following steps which are repeated for each one of the gates: determining a reliability of a subcircuit upstream from the gate consisting of the portions of the K branches located between the primary input and the gate, and the insertion of at least one arbiter at the gate forming a majority vote from the output signals of said portions of branches constituting the scanned subcircuit and outputting at least one majority signal to the respective inputs of an additional subcircuit formed b
    Type: Application
    Filed: November 29, 2013
    Publication date: October 15, 2015
    Applicant: ELECTRICITE DE FRANCE
    Inventors: Bastien Cousin, Gilles Deleuze, Laurent Cretinon, Gutemberg Goncalves Dos Santos, JR., Lirida Naviner