Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: Embodiments may relate to techniques or circuitry for the control of a clock signal by a phase-locked loop (PLL) circuit. The technique may include the identification of a first parameter related to a gain of a digitally controlled oscillator (DCO) and a second parameter related to a resolution of a time-to-digital converter (TDC). The technique may then include the identification of a third parameter related to filter coefficients of a loop filter of the PLL circuit based on the first and second parameter. The circuit may then output a clock signal based on the first, second, and third parameters. Other embodiments may be described or claimed.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Abstract: Embodiments may relate to techniques or circuitry for the control of a clock signal by a phase-locked loop (PLL) circuit. The technique may include the identification of a first parameter related to a gain of a digitally controlled oscillator (DCO) and a second parameter related to a resolution of a time-to-digital converter (TDC). The technique may then include the identification of a third parameter related to filter coefficients of a loop filter of the PLL circuit based on the first and second parameter. The circuit may then output a clock signal based on the first, second, and third parameters. Other embodiments may be described or claimed.

Abstract: TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.