Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.

Abstract: A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface.

Abstract: The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation.

Abstract: A light-trapping layer is integrated into a thin-film solar cell. It is integrated as a light-inlet layer, an intermediate layer or a shaded layer with nano-particles embedded in a transparent or non-transparent conductive film. Thus, light stays longer in an absorption layer with photocurrent increased; defects of interface between the absorption layer and the nano-material are decreased; anti-reflective effect to inlet light is enhanced; and a good integrity and a good reliability for long-time light-shining are obtained.

Abstract: A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response.

Abstract: A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response.

Abstract: The present electropolishing electrolyte comprises an acid solution and an alcohol additive having at least one hydroxy group, wherein the contact angle of the alcohol additive is smaller than the contact angle of the acid solution on a metal layer under electropolishing. The alcohol additive is selected methanol, ethanol and glycerol, and the acid solution comprises phosphoric acid. The volumetric ratio of glycerol to phosphoric acid is between 1:50 and 1:200, and is preferably 1:100. The volumetric ratio is between 1:100 and 1:150 for methanol to phosphoric acid, and between 1:100 and 1:150 for ethanol to phosphoric acid. In addition, the acid solution further comprises an organic acid selected from the group consisting of acetic acid and citric acid. The concentration is between 10000 and 12000 ppm for the acetic acid, and between 500 and 1000 ppm for citric acid.

Abstract: There is provided a silicon-based ferroelectric memory material, which includes a mesoporous silica with the nanopores thereon, and high-density arrays of nanocrystalline silicon or germanium quantum dots formed on the inner wall of the nanopores of the mesoporous silica. The silicon-based ferroelectric memory material is substantially composed of silicon and oxygen element, and the process for fabricating such a material is simple and can be done at the low temperature (<400° C.) so that the process for fabricating the silicon-based ferroelectric memory material is compatible with the semiconductor process, and is effective to prevent from cross pollution encountered in the prior art. The ferroelectric memory including the silicon-based ferroelectric memory material has the same advantages, such as high speed and long-life, as those of the conventional ferroelectric memory.

Abstract: An electropolishing process endpoint detection method is described. The method is applicable to the electropolishing of a metal layer under a fixed current or voltage, wherein a voltage current detector is installed in the electropolishing apparatus. When the electropolishing process is proceeded to the barrier layer, a noticeable change occurs to the electric current or electric voltage because the resistance of the barrier layer is different from that of the metal layer. Based on the change in the saturated current or voltage, the endpoint of the electropolishing process is detected. Further, the voltage or current supply is discontinued by feedback controlling the current or voltage and the electropolishing action is terminated.

Abstract: An electrolytic solution formulation for an electropolishing process comprises at least an acid solution and an organic additive. The acid solution includes phosphoric acid or a mixture of phosphoric acid and sulfuric acid solutions, which can form a passivation layer on the surface of the metal layer. The additive comprises at least an acid group, wherein the diffusion of the organic additive is controlled in which a concentration gradient is formed in the opening of the metal layer. The electropolishing rate at the top of the opening is thereby faster than that at the bottom of the opening. The organic additive is selected from a monocarboxylic acid compound, a dicarboxylic acid compound, a tricarboxylic acid compound, a heterocyclic carboxylic acid compound or a sulfonic acid compound.

Abstract: The present invention discloses a two-step CMP method and employed polishing compositions. In the first step, a first polishing slurry is provided to selectively polish the Al-alloy layer. Next, a second polishing slurry is provided to selectively polish the barrier layer. Accordingly, undesired surface non-planarity after the CMP process, such as metal dishing and corrosion of dielectric layers with complicated pattern geometry, can be avoided, and thus the planarization of wafer surfaces can be achieved.

Abstract: Slurry formulationf or CMP of organic-added low SOG dielectric was development. The SOG layers with various amount of organic content are subject to polish experiments using silica- and zirconia-based slurries with a variety of additives. The results indicate that, as the amount of organic content in SOG increases, CMP polish rate drops with silica-based KOH-added slurry. On the other hand, zirconia-based slurry could result in higher plish rate for both SOG (>400 nm/min) and thermal oxide. Polish selectivity ranging from 1.2 to 9.1 can be achieved by adding various amount of tetra-alkyl in ammonium hydroxide.

Abstract: An FET ROM and a manufacturing process in which ROM's can be stockpiled after the gates have been formed and the source and drain implants have been made but before the write operation has been performed. At this stage, the unwritten ROM has an array of enhancement mode FET's connected in a logical NAND configuration with an overlying layer of insulation. For a write operation, the insulation is removed to expose the drain and source regions of the FET's, a conductive layer is formed over the array, and the layer is selectively etched to leave a short circuit element between the drain and source of those FET's that are to store a binary 0 and to leave switchable the FET's that are to store a 1.