Patents by Inventor Bayu Thedjoisworo
Bayu Thedjoisworo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352497Abstract: A display may have one or more bent portions. To increase the magnitude of curvature in a display and/or to allow for compound curvature in the display, a display panel may be partially formed in a planar state. The partial display panel is then bent to have desired curvature. After the partial display panel is bent, additional display components that are susceptible to damage during the bending process may be added to complete the display panel. A flexible printed circuit may be formed directly on the display panel using precise deposition of conductive material. By forming the flexible printed circuit layer-by-layer directly on the display panel, no substantive pressure needs to be applied to the display panel. Electrical connections may therefore be made to the display panel in regions of the display with high levels of curvature and/or with compound curvature without causing front-of-screen artifacts for the display panel.Type: ApplicationFiled: March 1, 2023Publication date: November 2, 2023Inventors: Meng-Tse Chen, Anshi Liang, Arnoldus A Barlian, Bayu A Thedjoisworo, Boris A Russ, Chun-Hsien Lee, Chun-Lan Wu, Han-Chieh Chang, Jiming Yu, Marc J DeVincentis, Nathan K Gupta, Paolo Sacchetto, Paul S Drzaic, Zhen Zhang, Ziyang Zhang
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Publication number: 20230343914Abstract: Conductive traces may be conformally wrapped around the side of a display panel that includes an array of display pixels. The conductive traces may electrically connect contacts on an upper surface of the display panel to corresponding contacts on a flexible printed circuit that is attached to a lower surface of the display panel. The side-wrapped conductive traces may be interposed between first and second insulating layers. The flexible printed circuit may have a multi-step interface that is electrically connected to the side-wrapped conductive traces. A system-in-package including a display driver integrated circuit may be mounted to the flexible printed circuit. The system-in-package may include a plurality of redistribution layers that electrically connect contacts on the display driver integrated circuit to contacts on the flexible printed circuit.Type: ApplicationFiled: March 16, 2023Publication date: October 26, 2023Inventors: Han-Chieh Chang, Anshi Liang, Arnoldus A Barlian, Bayu A Thedjoisworo, Boris A Russ, Chun-Lan Wu, Ken Hsuan Liao, Marc J DeVincentis, Meng-Tse Chen, Nathan K Gupta, Paolo Sacchetto, Paul S Drzaic, Po-Jui Chen, Ying-Chih Wang, Yong Sun, Zhen Zhang, Ziyang Zhang
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Patent number: 9613825Abstract: Provided herein are methods and apparatus of hydrogen-based photoresist strip operations that reduce dislocations in a silicon wafer or other substrate. According to various embodiments, the hydrogen-based photoresist strip methods can employ one or more of the following techniques: 1) minimization of hydrogen budget by using short processes with minimal overstrip duration, 2) providing dilute hydrogen, e.g., 2%-16% hydrogen concentration, 3) minimization of material loss by controlling process conditions and chemistry, 4) using a low temperature resist strip, 5) controlling implant conditions and concentrations, and 6) performing one or more post-strip venting processes. Apparatus suitable to perform the photoresist strip methods are also provided.Type: GrantFiled: August 20, 2012Date of Patent: April 4, 2017Assignee: Novellus Systems, Inc.Inventors: Roey Shaviv, Kirk Ostrowski, David Cheung, Joon Park, Bayu Thedjoisworo, Patrick J. Lord
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Patent number: 9558928Abstract: Method and apparatus for cleaning a substrate having a plurality of high-aspect ratio openings are disclosed. A substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures having alternating layers of oxide and nitride or alternating layers of oxide and polysilicon. The substrate can include a silicon oxide layer over a damaged or amorphous silicon layer in the high-aspect ratio openings. To remove the silicon oxide layer, a bias power can be applied in the plasma processing chamber at a low pressure, and a fluorine-based species can be used to etch the silicon oxide layer. To remove the underlying damaged or amorphous silicon layer, a source power and a bias power can be applied in the plasma processing chamber, and a hydrogen-based species can be used to etch the damaged or amorphous silicon layer.Type: GrantFiled: December 19, 2014Date of Patent: January 31, 2017Assignee: Lam Research CorporationInventors: Bayu Thedjoisworo, Helen Zhu, Linda Marquez, Joon Park
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Publication number: 20160064212Abstract: Method and apparatus for cleaning a substrate having a plurality of high-aspect ratio openings are disclosed. A substrate can be provided in a plasma processing chamber, where the substrate includes the plurality of high-aspect ratio openings, the plurality of high-aspect ratio openings are defined by vertical structures having alternating layers of oxide and nitride or alternating layers of oxide and polysilicon. The substrate can include a silicon oxide layer over a damaged or amorphous silicon layer in the high-aspect ratio openings. To remove the silicon oxide layer, a bias power can be applied in the plasma processing chamber at a low pressure, and a fluorine-based species can be used to etch the silicon oxide layer. To remove the underlying damaged or amorphous silicon layer, a source power and a bias power can be applied in the plasma processing chamber, and a hydrogen-based species can be used to etch the damaged or amorphous silicon layer.Type: ApplicationFiled: December 19, 2014Publication date: March 3, 2016Inventors: Bayu Thedjoisworo, Helen Zhu, Linda Marquez, Joon Park
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Patent number: 9034773Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.Type: GrantFiled: June 12, 2013Date of Patent: May 19, 2015Assignee: Novellus Systems, Inc.Inventors: Bayu Thedjoisworo, David Cheung, Joon Park
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Publication number: 20150075715Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.Type: ApplicationFiled: November 19, 2014Publication date: March 19, 2015Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
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Patent number: 8916477Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.Type: GrantFiled: June 12, 2013Date of Patent: December 23, 2014Assignee: Novellus Systems, Inc.Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
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Publication number: 20140004707Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.Type: ApplicationFiled: June 12, 2013Publication date: January 2, 2014Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
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Publication number: 20140004708Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.Type: ApplicationFiled: June 12, 2013Publication date: January 2, 2014Inventors: Bayu Thedjoisworo, David Cheung, Joon Park
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Publication number: 20130048014Abstract: Provided herein are methods and apparatus of hydrogen-based photoresist strip operations that reduce dislocations in a silicon wafer or other substrate. According to various embodiments, the hydrogen-based photoresist strip methods can employ one or more of the following techniques: 1) minimization of hydrogen budget by using short processes with minimal overstrip duration, 2) providing dilute hydrogen, e.g., 2%-16% hydrogen concentration, 3) minimization of material loss by controlling process conditions and chemistry, 4) using a low temperature resist strip, 5) controlling implant conditions and concentrations, and 6) performing one or more post-strip venting processes. Apparatus suitable to perform the photoresist strip methods are also provided.Type: ApplicationFiled: August 20, 2012Publication date: February 28, 2013Inventors: Roey Shaviv, Kirk Ostrowski, David Cheung, Joon Park, Bayu Thedjoisworo, Patrick J. Lord