Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.

Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.

Abstract: A dual-band antenna module includes a first antenna structure and a second antenna structure. The first antenna structure includes a first insulating substrate, a conductive metal layer, a plurality of grounding supports, and a first feeding pin. The second antenna structure includes a second insulating substrate, a top metal layer, a bottom metal layer, and a second feeding pin. The conductive metal layer is disposed on the first insulating substrate. The grounding supports are configured for supporting the first insulating substrate. The second insulating substrate is disposed above the first insulating substrate. The top metal layer and the bottom metal layer are respectively disposed on a top side and a bottom side of the second insulating substrate. The first frequency band signal transmitted or received by the first antenna structure is smaller than the second frequency band signal transmitted or received by the second antenna structure.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A lithium-ion battery and methods thereof are disclosed. In an aspect, the lithium-ion battery includes an anode component, a cathode component, a separator, and an electrolyte. The anode component includes an anode current collector and a respective anode coating on each side of the anode current collector. An anode coating includes composite particles including carbon and silicon. A mass fraction of the silicon in the composite particles of the anode coatings may be in a range of about 5 wt. % to about 70 wt. % of the anode coatings. The anode component undergoes a maximum areal expansion (Amax) during the multiple charging and discharging cycles. The anode current collector comprises a copper foil, the copper foil being characterized, before the respective anode coatings are formed thereon, by an ultimate tensile stress (UTS) and a strain at the UTS (?UTS).

Abstract: A sprayer, comprising: a container, configured to contain liquid; a passage, comprising a first opening, a second opening, a resonator and a mesh, when the liquid is passed through the resonator, the liquid is emitted as a gas; a first optical sensor, configured to sense first optical data of at least portion of the mesh or at least portion of a surface of the container; and a processing circuit, configured to compute a foaming level of the mesh or of the surface according to the first optical data, and configured to determine whether the resonator should be turned off or not according to the foaming level. In another aspect, the processing circuit estimates a liquid level of the liquid but does not correspondingly turn off the resonator. By this way, the resonator may be turned on or turned off more properly and the liquid level may be more precisely estimated.

Abstract: An electronic device and a related tiled electronic device are disclosed. The electronic device includes a protective layer, a circuit structure, a sensing element and a control unit. The circuit structure is disposed on the protective layer and surrounds the sensing element. The control unit is disposed between the circuit structure and the protective layer and electrically connected to the sensing element. The protective layer surrounds the control unit and contacts a surface of the circuit structure.

Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.

Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: An optical structure film and a light source module are provided. The optical structure film includes multiple optical unit microstructures. Each of the optical unit microstructures has four side surfaces and an inwardly concave beam splitting surface. The beam splitting surface is respectively connected to the side surfaces, and the beam splitting surface has four endpoints when viewed from a front viewing angle. Connection lines of the four endpoints form a rectangle. The beam splitting surface includes at least one beam splitting curved surface. A junction of the at least one beam splitting curved surface and one of the four side surfaces is a first line segment. A projection of a midpoint of an edge of the rectangle on the beam splitting surface overlaps with a relative extreme point of the first line segment.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.