Patents by Inventor Be-Shan TSENG
Be-Shan TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968831Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.Type: GrantFiled: September 14, 2022Date of Patent: April 23, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Be-Shan Tseng
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Publication number: 20230363160Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The gate composite stack structure disposed on the dielectric substrate in a first region and a second region of the dielectric substrate. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Meng-Yen Wu, Pi-Shan Tseng
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Publication number: 20230363159Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Applicant: MACRONIX International Co., Ltd.Inventor: Pi-Shan Tseng
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Publication number: 20230240071Abstract: Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Applicant: MACRONIX International Co., Ltd.Inventor: Pi-Shan Tseng
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Publication number: 20230077489Abstract: A 3D AND flash memory device includes a gate stack structure, a plurality of channel pillars, a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of charge storage structures, and a plurality of isolation walls. The gate stack structure is located on a dielectric substrate and includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other. The channel pillars pass through the gate stack structure. The first conductive pillars and the second conductive pillars are located in the channel pillars and are electrically connected to the channel pillars. The charge storage structures are located between the gate layers and the channel pillar. The isolation walls are buried in the gate layers and cover the charge storage structures at outer sidewalls of the second conductive pillars.Type: ApplicationFiled: September 16, 2021Publication date: March 16, 2023Applicant: MACRONIX International Co., Ltd.Inventors: Min-Feng Hung, Pi-Shan Tseng
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Publication number: 20230005951Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Inventor: Be-Shan TSENG
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Patent number: 11476271Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.Type: GrantFiled: November 4, 2020Date of Patent: October 18, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Be-Shan Tseng
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Publication number: 20220139947Abstract: A memory device includes a substrate, a first dielectric structure, a second dielectric structure, a channel structure, a source structure, and a drain structure. The first dielectric structure and the second dielectric structure are disposed on the substrate, and are spaced apart from each other in a first direction. The channel structure interconnects the first dielectric structure and the second dielectric structure. The source structure and the drain structure are on opposite ends of the channel structure, and are respectively embedded in the first dielectric structure and the second dielectric structure, wherein a ratio in length along the first direction of the source structure to the first dielectric structure is between 0.3 and 0.4.Type: ApplicationFiled: November 4, 2020Publication date: May 5, 2022Inventor: Be-Shan TSENG
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Patent number: 9899369Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.Type: GrantFiled: September 22, 2015Date of Patent: February 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Publication number: 20170084604Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: Pei-Shan Tseng, Yu-Cheng Liao, Ping-Chen Chang, Tien-Hao Tang, Kuan-Cheng Su
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Patent number: 8981521Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.Type: GrantFiled: August 23, 2013Date of Patent: March 17, 2015Assignee: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
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Publication number: 20150054132Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: United Microelectronics Corp.Inventors: Chang-Tzu Wang, Pei-Shan Tseng, Tien-Hao Tang
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Publication number: 20140264726Abstract: A semiconductor device is provided having reduced corner thinning in a shallow trench isolation (STI) structure of the periphery region. The semiconductor device may be substantially free of any corner thinning at a corner of a STI structure of the periphery region. Methods of manufacturing such a semiconductor device are also provided.Type: ApplicationFiled: June 18, 2013Publication date: September 18, 2014Inventors: Yao-Fu Chan, Ta-Kang Chu, Pi-Shan Tseng
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Patent number: 8062536Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: March 22, 2010Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Publication number: 20100173490Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: ApplicationFiled: March 22, 2010Publication date: July 8, 2010Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7718079Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: November 20, 2001Date of Patent: May 18, 2010Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Publication number: 20090165282Abstract: A method of manufacturing a bezel for LCD/LED panel comprises the first step of material feeding, wherein a roll of wide metal material is fed intermittently and cut into rectangular metal-plate components, and two rolls of narrow metal material with an appropriate spacing therebetween are fed to a welding table; each of the rectangular metal-plate components is tightly welded at two ends thereof with inner edges of the two rolls of narrow metal material respectively; cutting is executed to produce a planar frame at an interval of an appropriate distance within which one or two rectangular metal-plate components are welded, and then inner and outer edges of the planar frame are squarely trimmed to conform to correct dimensions and shape; lastly, outer margins of the planar frame are pressed and bent downward to form bent portions, thereby completing a final product of the bezel for LCD/LED panel.Type: ApplicationFiled: January 30, 2008Publication date: July 2, 2009Inventor: Shu-Shan Tseng
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Patent number: 7514014Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: April 11, 2000Date of Patent: April 7, 2009Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, W. B. Shieh, J. Y. Wu, Water Lur, Shih-Wei Sun
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Patent number: 7271101Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: December 22, 2005Date of Patent: September 18, 2007Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7078346Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: July 29, 2004Date of Patent: July 18, 2006Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun