Patents by Inventor Be Ware

Be Ware has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8924680
    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: December 30, 2014
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Frederick A. Ware
  • Publication number: 20140376324
    Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 25, 2014
    Applicant: Rambus Inc.
    Inventors: Thomas Vogelsang, William N. Ng, Frederick A. Ware
  • Publication number: 20140374416
    Abstract: The present disclosure, in one embodiment, relates to a liner-based assembly having an overpack and a liner disposed within the overpack. The liner may be formed by blow molding a liner preform within the overpack to form a blow molded liner substantially conforming to the interior of the overpack and generally forming an interface with an interior of the overpack. The present disclosure, in another embodiment, relates to a liner-based assembly including a blow-molded overpack comprised of polyethylene terephthalate, a blow-molded liner disposed within the overpack, the liner comprised of a polymer material, wherein the overpack and liner have a combined wall thickness of about 0.3 mm or less, and a base cup configured to at least partially surround an exterior of the overpack. In some embodiments, the liner has a volume of up to about 4.7 liters and an empty weight of between about 260-265 grams.
    Type: Application
    Filed: December 20, 2012
    Publication date: December 25, 2014
    Inventors: Glenn Tom, Greg Nelson, Wei Liu, Amy Koland, Don Ware, Alfredo Daniel Botet, Jordan Henery Hodges, Eric J. Brunella, Chantel Roush, Daniel J. Durham, Tracy M. Momany, Thomas J. Carros
  • Patent number: 8918669
    Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: December 23, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Patent number: 8918703
    Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: December 23, 2014
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
  • Patent number: 8918667
    Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: December 23, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
  • Patent number: 8916277
    Abstract: Wallboards, as well as other building materials, are produced by methods which use significantly reduced embodied energy, generating far less greenhouse gases when compared with the energy used to fabricate gypsum wallboard. A novel cementitious core, consisting in one embodiment of post-industrial waste such as slag and combined with pH modifiers, provides a controlled exothermic reaction to create a gypsum-wallboard-like core which can be wrapped in a selected material such as recycled paper and manufactured on a conveyor system to appear, weigh and handle similar to gypsum wallboard, but without the large amounts of energy required to make gypsum wallboard. The manufacturing process results in lower greenhouse gas emissions than the processes used to make gypsum wallboard.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 23, 2014
    Assignee: Serious Energy, Inc.
    Inventors: Kevin Surace, Meredith Ware, Denise Hoover, Jiaping Han, Tiandan Chen
  • Patent number: 8913746
    Abstract: A method of commissioning wireless network devices in a communication network includes assigning a user-defined number to a wireless network device. The method further includes generating, by the wireless network device, an identification number based on the user-defined number using a first hashing algorithm, generating, by the wireless network device, an encryption key based on the user-defined number using a second hashing algorithm, and transmitting, by the wireless network device, a message that is encrypted using the encryption key for joining the wireless network device to the communication network. The user-defined number is to be provided by a user using an input device that is coupled to, or integral to, the wireless network device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 16, 2014
    Assignee: Schneider Electric IT Corporation
    Inventors: Gary Ware, John R. Van Hook, Tiegeng Ren
  • Patent number: 8908466
    Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
  • Patent number: 8909383
    Abstract: A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Scott J. Hadderman, Daniel J. Kearney, Wei Huang, K. Paul Muller, William J. Rooney, Guillermo J. Silva, Malcolm S. Ware, Emmanuel Yashchin, Peter B. Yocom
  • Patent number: 8909954
    Abstract: A mechanism is provided for dynamically changing power caps for a set of powered elements. Current being consumed by the set of powered elements P on a branch circuit is measured and available current on the branch circuit is determined. A new total power cap for a current time period t is identified based on a current total power cap and the measured current. A difference in total power caps (?TPC) is determined and, for each powered element p in the set of powered elements P at the current time period, a new power cap PC (p,t) is determined based on the previous power cap PC(p,t?1) and the difference of the total power caps to the set of powered elements P. A power cap of each powered element p is then dynamically set to the new power cap PC (p,t).
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Thomas M. Brey, Wael R. El-Essawy, Alexandre P. Ferreira, Thomas W. Keller, Jr.
  • Patent number: 8899327
    Abstract: A method for recovering oil from a reservoir comprises performing a first CHOPS process in one or more first wells, performing a second CHOPS process in one or more second wells that are laterally offset from the first wells, and injecting gas and/or steam into the one or more second wells after the CHOPS processes are at least partially completed. A plurality of channels that extend from the one or more first and second wells may be created as a result of the CHOPS processes. The gas and/or steam may be injected into the channels of the one or more second wells via a downhole steam generator that is located in the one or more second wells. The gas and/or steam may form a gas and/or steam front that drives reservoir products into the channels of the one or more first wells. The reservoir products may be recovered to the surface through the one or more first wells.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 2, 2014
    Assignee: World Energy Systems Incorporated
    Inventors: Myron I. Kuhlman, Charles H. Ware
  • Publication number: 20140347329
    Abstract: Embodiments of the present invention generally relate to methods and systems for correcting position and orientation displacement for a freehand user input device. Systems and methods include measuring the position and orientation of a freehand user input device over a period of time, determining the position and orientation as related to a specific time point at activation of a button, applying a temporal offset to the time point of the activation of the button to determine a button press start time, determining the position and orientation in the virtual space associated with the button press start time and associating the button press to the position and orientation in the virtual space.
    Type: Application
    Filed: November 16, 2012
    Publication date: November 27, 2014
    Inventor: John C. Ware
  • Publication number: 20140345834
    Abstract: A heat exchanger assembly for an electronic image assembly placed within a housing where ambient air surrounds the exterior of the housing and a rear plate may be placed behind a backlight to create a channel. An ambient air fan may be placed between two portions of a heat exchanger to force ambient air through the heat exchanger. The fan may also be positioned to also force ambient air through the channel. A circulating gas fan may also be placed within the housing to force circulating gas through at least one portion of the heat exchanger.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: William Dunn, Tim Hubbard, Ware Bedell
  • Publication number: 20140351673
    Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Brent Haukness, Scott C. Best, Wayne F. Ellis
  • Publication number: 20140351629
    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 8893713
    Abstract: A solar concentrator assembly can include mirror assemblies that are connected to pivotable frames with locating connections. The locating connections can be in the form of cam devices or tool-less connections formed by snap fitting devices as well as tool-less cam devices.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 25, 2014
    Assignee: Sunpower Corporation
    Inventors: Brian Wares, Charles Almy, Nicholas Barton
  • Publication number: 20140344546
    Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
  • Publication number: 20140341872
    Abstract: Compositions and methods are disclosed for improving food safety. One or more lactic acid producing microorganisms are shown to inhibit pathogenic contaminations on food materials. The lactic acid producing microorganisms are capable of adhering to various surfaces and may serve as a bio-sanitizing agent (or bio-sanitizer). Lactic acid producing microorganisms or cell free extract of these microorganisms may be used in an effective and natural method to prevent L. monocytogenes infection in food products, as well as in food processing facilities and equipments.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 20, 2014
    Applicant: Guardian Food Technologies, LLC
    Inventors: Douglas R. Ware, Philip G. Crandall, Steven C. Ricke
  • Publication number: 20140334238
    Abstract: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state.
    Type: Application
    Filed: February 5, 2014
    Publication date: November 13, 2014
    Applicant: RAMBUS INC.
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel