Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.

Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.

Abstract: A technique for dynamic dispatch involves adapting a method at a dispatch point to reference a state cache. State of the state cache may be associated with an object type and a method signature. When a method is adapted at the dispatch point to reference a state cache, the reference is to a state cache associated with a state that matches the method signature and the object type of the object dispatched upon. The state cache may be shared among multiple methods with similar associated states to reduce memory requirements.

Abstract: The present invention is a new method and apparatus to perform fast compilation of platform independent bytecode instruction listings into high quality machine code in a single sequential pass. More specifically, the present invention creates a new method and apparatus for the translation of platform neutral bytecode into high quality machine code in a single sequential pass in which information from the preceding instruction translation is used to mimic an optimizing compiler without the extensive memory and time requirements. Where the preceding instruction translation cannot be used due to no direct control flow, information from comprehensive stack maps is then used.

Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.

Abstract: A technique for dynamic dispatch involves adapting a method at a dispatch point to reference a state cache. State of the state cache may be associated with an object type and a method signature. When a method is adapted at the dispatch point to reference a state cache, the reference is to a state cache associated with a state that matches the method signature and the object type of the object dispatched upon. The state cache may be shared among multiple methods with similar associated states to reduce memory requirements.

Abstract: A technique for dynamically relocating an object during garbage collection involves guaranteeing bounds on thread pause times. A process according to the technique may include pausing threads, bounding pause times by scanning only one of a plurality of threads, and resuming the threads. Another process according to the technique may include suspending a plurality of threads, relocating an object to a new memory location, updating references associated with an old memory location for only one of the threads such that the references are associated with the new memory location, and resuming the threads. In an embodiment, the process may include initially marking each of the threads “unscanned.” In another embodiment, the process may include reading the object from the first memory location and writing the object to the second memory location. An example system according to the technique may include a scheduler and a relocation engine.

Abstract: A technique for sharing code fragments involves detecting identical code fragments, then replacing code fragments with references to an identical code fragment. A process according to the technique may include detecting identical code fragments in one or more modules, presenting at runtime a single code fragment that is identical to the identical code fragments, and automatically sharing the single code fragment among the one or more modules. A system according to the technique may include a code fragments database that may includes code fragments and a code server configured to receive requests for a program and provide references to one or more of the code fragments in the code fragments database. Another system according to the technique may include a first object, a second object, and a method object, wherein a reference associated with a first method of the first object and the reference associated with a second method of the second object are pointers to the method object.

Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.

Abstract: The present invention is a new method and apparatus to perform fast compilation of platform independent bytecode instruction listings into high quality machine code in a single sequential pass. More specifically, the present invention creates a new method and apparatus for the translation of platform neutral bytecode into high quality machine code in a single sequential pass in which information from the preceding instruction translation is used to mimic an optimizing compiler without the extensive memory and time requirements. Where the preceding instruction translation cannot be used due to no direct control flow, information from comprehensive stack maps is then used.

Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.