Patents by Inventor Beate Frankowsky

Beate Frankowsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7007260
    Abstract: A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on respectively different layer types. In this manner, the at least two different wiring forms can be individually and jointly analyzed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: February 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Helge Altfeld, Monika Gschöderer, Michael Eisenhut, Marc Walter, Beate Frankowsky
  • Publication number: 20050144583
    Abstract: Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar is applied on a mask in addition to a main structure for the purpose of a subsequent imaging of the main structure from the mask onto a substrate by exposure. At least one correction value for the OPC is selected in a particular manner in dependence upon a spacing between two parts of the main structure or a spacing between neighboring main structures and the presence of a scatter bar between the two parts of the main structure. The manner in which the correction value is defined is determined by so forming an auxiliary quantity for each scatter bar, that the largest auxiliary quantity that is set is less than the smallest spacing between the parts of the main structure, so that in a program for OPC the presence of a scatter bar between the two parts of the main structure is suggested.
    Type: Application
    Filed: January 10, 2005
    Publication date: June 30, 2005
    Inventor: Beate Frankowsky
  • Patent number: 6902854
    Abstract: Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar in applied on a mask in addition to a main structure for the purpose of a subsequent imaging of the main structure from the mask onto a substrate by exposure. At leant one correction value for the OPC is selected in a particular manner in dependence upon a spacing between two parts of the main structure or spacing between neighboring main structures and the presence of a scatter bar between the two parts of the main structure. The manner in which the correction value is defined is determined by so forming an auxiliary quantity for each scatter bar, that the largest auxiliary quantity that is set is less than the smallest spacing between the parts of the main structure, so that in a program for OPC the presence of a scatter bar between the two parts of the main structure is suggested.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: June 7, 2005
    Assignee: Infineon Technologies AG
    Inventor: Beate Frankowsky
  • Patent number: 6571383
    Abstract: A method of fabricating a semiconductor device is outlined in FIG. 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A first pass corrected pattern is then derived by correcting the ideal patterns for major effects, e.g., aerial image effects (315, 320). A second pass corrected pattern is then derived by correcting the first pass corrected patterns for remaining errors (304). The second pass corrected pattern can be used to build a photomask (345). The photomask can then be used to produce a semiconductor device, such a memory chip or logic chip (350).
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 27, 2003
    Assignee: Infineon Technologies, AG
    Inventors: Shahid Butt, Henning Haffner, Beate Frankowsky
  • Publication number: 20030079196
    Abstract: A method for fabricating an integrated semiconductor circuit having at least two different wiring forms realized in a same metallization plane includes drawing each of the different wiring forms on respectively different layer types. In this manner, the at least two different wiring forms can be individually and jointly analyzed.
    Type: Application
    Filed: October 18, 2002
    Publication date: April 24, 2003
    Inventors: Helge Altfeld, Monika Gschoderer, Michael Eisenhut, Marc Walter, Beate Frankowsky
  • Publication number: 20020182523
    Abstract: Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar is applied on a mask in addition to a main structure for the purpose of a subsequent imaging of the main structure from the mask onto a substrate by exposure. At least one correction value for the OPC is selected in a particular manner in dependence upon a spacing between two parts of the main structure and the presence of a scatter bar between the two parts of the main structure. The manner in which the correction value is defined is determined by so forming an auxiliary quantity for each scatter bar, that the largest auxiliary quantity that is set is less than the smallest spacing between the parts of the main structure, so that in a program for OPC the presence of a scatter bar between the two parts of the main structure is suggested. In tis way, correction values for a rule-based OPC method are flexibly defined even in the presence of scatter bars.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 5, 2002
    Inventor: Beate Frankowsky