Abstract: According to some embodiments, a shared new data and swap input line adapted to receive a shared new data and swap bit and an output bit that is the shared new data and swap bit is provided.

Abstract: A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.

Abstract: According to some embodiments, a shared new data and swap bit is provided for an encryption core.

Abstract: According to some embodiments, an encryption key is shifted in either a first or second direction via a uni-directional shifting unit.

Abstract: According to some embodiments, a shared control and information bit can represent either an encryption key position selection or a new encryption key value.

Abstract: According to some embodiments, a cipher block chaining unit is provided to support multiple encryption cores.

Abstract: A method of transposing an array using diagonal access. An array of m rows, m diagonals up, and m diagonals down. Rows and diagonals access the same array using different mapping functions. Each row comprising n data element. Each diagonal comprising of n data element. First, every row of the array is loaded into the diagonals up with same index number in a new storage array. Second, every row of the new array is rotated by its index number. Third, the new array is stored back in the original array using the diagonals down. The result, a transposed array of the original array is completed.

Abstract: To improve data encryption and/or decryption, look-up tables in the field programmable gate array are used to store preselected values for the substitution box used in many encryption/decryption schemes. Utilizing look-up tables in such a manner reduces the overall gate count in the FPGA device resulting in quicker speeds, lower power consumption, and the ability to reconfigure the device for different encryption/decryption implementations.

Abstract: A data encryption/decryption circuit is presented that can be implemented in a field programmable gate array. First and second logic components are provided which are controlled by first and second control signal to direct data between memory and a data processing core (e.g., a DES or TDES processing core). In a ECB mode of operation, the logic components simply pass the data from the memory to the data processing core and from the data processing core to the memory. In CBC mode, the data from the memory is XORed with data from the appropriate data processing core in the first logic component during an encryption operation, and in the second logic component during a decryption operation.

Abstract: To improve data encryption and/or decryption, data can be preloaded into an alternate storage area during a time that a data encryption/decryption operation is being performed. For example, while data in a first storage area is being encrypted or decrypted by a TDES processing core in a field programmable gate array, data can be loaded into a second storage area so that as soon as the data in the first storage area is encrypted/decrypted, the processing core can move on to the next set of data. While the data in the second storage area is being encrypted/decrypted, the data in the first storage area can be moved out and replaced with new data for the next data encryption/decryption operation.