Patents by Inventor Bee Liang Catherine NG

Bee Liang Catherine NG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package and method of packaging semiconductor devices
    Patent number: 8647924
    Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: February 11, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chin Hock Toh, Keng Yuen Au, Reynaldo Vincent Hernandez Sta Agueda, Bee Liang Catherine Ng, Librado Amurao Gatbonton, Xue Ren Zhang, Yi-Sheng Anthony Sun
  • SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20100261313
    Abstract: A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 14, 2010
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chin Hock TOH, Keng Yuen AU, Reynaldo Vincent Hernandez STA AGUEDA, Bee Liang Catherine NG, Librado Amurao GATBONTON, Xue Ren ZHANG, Yi-Sheng Anthony SUN