Patents by Inventor Been-Der Chen

Been-Der Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119582
    Abstract: Described are embodiments for generating a post-optical proximity correction (OPC) result for a mask using a target pattern and reference layer patterns. Images of the target pattern and reference layers are provided as an input to a machine learning (ML) model to generate a post-OPC image. The images may be input separately or combined into a composite image (e.g., using a linear function) and input to the ML model. The images are rendered from pattern data. For example, a target pattern image is rendered from a target pattern to be printed on a substrate, and a reference layer image such as dummy pattern image is rendered from dummy pattern. The ML model is trained to generate the post-OPC image using multiple images associated with target patterns and reference layers, and using a reference post-OPC image of the target pattern. The post-OPC image may be used to generate a post-OPC mask.
    Type: Application
    Filed: January 31, 2022
    Publication date: April 11, 2024
    Inventors: Quan ZHANG, Been-Der CHEN, Wei-chun Fong, Zhangnan ZHU, Robert Elliott BOONE
  • Publication number: 20240095437
    Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.
    Type: Application
    Filed: October 23, 2023
    Publication date: March 21, 2024
    Applicant: ASML Netherlands B.V.
    Inventors: Quan ZHANG, Yong-Ju Cho, Zhangnan Zhu, Boyang Huang, Been-Der Chen
  • Patent number: 11797748
    Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: October 24, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Quan Zhang, Yong-Ju Cho, Zhangnan Zhu, Boyang Huang, Been-Der Chen
  • Patent number: 11734490
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 22, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Quan Zhang, Been-Der Chen, Rafael C. Howell, Jing Su, Yi Zou, Yen-Wen Lu
  • Publication number: 20230044490
    Abstract: A method of determining a mask pattern for a target pattern to be printed on a substrate. The method includes partitioning a portion of a design layout including the target pattern into a plurality of cells with reference to a given location on the target pattern; assigning a plurality of variables within a particular cell of the plurality of cells, the particular cell including the target pattern or a portion thereof; and determining, based on values of the plurality of variables, the mask pattern for the target pattern such that a performance metric of a patterning process utilizing the mask pattern is within a desired performance range.
    Type: Application
    Filed: November 21, 2020
    Publication date: February 9, 2023
    Inventors: Quan ZHANG, Tatung CHOW, Been-Der CHEN, Yen-Wen LU
  • Publication number: 20220121804
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: ASML NETHERLAND B.V.
    Inventors: Quan Zhang, Been-Der Chen, Rafael C. Howell, Jing Su, Yi Zou, Yen-Wen Lu
  • Publication number: 20220100079
    Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 31, 2022
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Quan ZHANG, Yong-Ju CHO, Zhangnan ZHU, Boyang HUANG, Been-Der CHEN
  • Patent number: 11232249
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 25, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Quan Zhang, Been-Der Chen, Rafael C. Howell, Jing Su, Yi Zou, Yen-Wen Lu
  • Patent number: 11176307
    Abstract: A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 16, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Venugopal Vellanki, Been-Der Chen
  • Publication number: 20200380362
    Abstract: Methods of training machine learning models related to a patterning process, including a method for training a machine learning model configured to predict a mask pattern. The method including obtaining (i) a process model of a patterning process configured to predict a pattern on a substrate, wherein the process model comprises one or more trained machine learning models, and (ii) a target pattern, and training the machine learning model configured to predict a mask pattern based on the process model and a cost function that determines a difference between the predicted pattern and the target pattern.
    Type: Application
    Filed: February 20, 2019
    Publication date: December 3, 2020
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Yu CAO, Ya LUO, Yen-Wen LU, Been-Der CHEN, Rafael C. HOWELL, Yi ZOU, Jing SU, Dezheng SUN
  • Publication number: 20200193080
    Abstract: A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.
    Type: Application
    Filed: November 13, 2017
    Publication date: June 18, 2020
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Venugopal VELLANKI, Been-Der CHEN
  • Publication number: 20200050099
    Abstract: A method including: obtaining a portion of a design layout; determining characteristics of assist features based on the portion or characteristics of the portion; and training a machine learning model using training data including a sample whose feature vector includes the characteristics of the portion and whose label includes the characteristics of the assist features. The machine learning model may be used to determine characteristics of assist features of any portion of a design layout, even if that portion is not part of the training data.
    Type: Application
    Filed: May 4, 2018
    Publication date: February 13, 2020
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jing SU, Yi ZOU, Chenxi LIN, Yu CAO, Yen-Wen LU, Been-Der CHEN, Quan ZHANG, Stanislas Hugo Louis BARON, Ya LUO
  • Patent number: 9619607
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 11, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jun Tao, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Patent number: 9418194
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 16, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8938699
    Abstract: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: January 20, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: William S. Wong, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Tatsuo Nishibe
  • Publication number: 20140359543
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Applicant: ASML Netherlands B.V.
    Inventors: Jun TAO, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Publication number: 20140351772
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Taihui LIU, Been-Der CHEN, Yen-Wen LU
  • Patent number: 8826198
    Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Min-Chun Tsai, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8812998
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 19, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Tao, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Patent number: 8806389
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: August 12, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu