Abstract: In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.

Abstract: In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.

Abstract: In one embodiment of the invention, a NOR Flash memory includes a buried source rail that directly connects to a source strap. Furthermore, a drain plug connects directly to a bit line.

Abstract: A method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing includes depositing a gate polysilicon layer on a semiconductor substrate which has a field oxide isolation structure, and then performing a polysilicon chemical-mechanical polishing after a gate polysilicon layer is deposited in order to smooth the uneven polysilicon surface resulting from the field oxide isolation structure so as to lessen the next lithography process fault because of the non-flatness.

Abstract: A method of patterning a conductive structure includes providing a semiconductor substrate, forming a conductive layer on the semiconductor substrate, forming a hard mask layer on the conductive layer and forming a photo-resist layer on the hard mask layer. An isotropic etching is applied to remove a partial region of the photo-resistant layer in order to form a patterned photo-resistant layer. Then, the patterned photo-resistant layer is used as a mask to form a patterned hard mask layer by etching the hard mask layer. Next, the patterned hard mask layer is used as another mask to remove the partial region of the conductive layer to form a patterned conductive layer. The patterned photo-resist layer is only used for etching the hard mask layer, therefore it is able to enhance the resolution when using a thinner photo-resistant layer, furthermore to fabricate a patterned conductive layer with a miniaturized dimensional structure.

Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

Abstract: A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface of the shallow trench. Then, the silicon nitride mask layer will be etched to reveal the corner. Finally, a layer of oxide is formed on the base to fill up the trench so that the trench isolation device can be completed. The present invention is designed to solve the corner recess problem, reduce generation of kick effect, and enhance the device characteristics and electrical quality.

Abstract: A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).

Abstract: A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).

Abstract: A method for improving the flatness of an oxide layer comprising the steps of providing a semiconductor structure, forming a polysilicon layer on the semiconductor structure, utilizing chemical mechanical polishing to planarize the polysilicon layer, and forming an oxide layer on the polysilicon layer. As a result of using chemical mechanical polishing on the polysilicon layer, an improved flatness of the subsequently formed oxide layer is achieved.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash contactless EPROM or EEPROM type. The array of memory cells in these devices have elongated, parallel source and drain regions disposed beneath field oxide regions. The word lines are elongated, parallel strips of polysilicon. A series of SiO.sub.2 depositions using TEOS chemistry in a PECVD process, and etches using sputter etch and plasma processes, is performed. After deposition and etchback, the polysilicon word lines remain exposed while all previous exposed substrate regions between source and drain are covered with SiO.sub.2. A metal deposition and silicidation are performed forming a silicide on the exposed silicon word lines thereby lowering the resistance of the word lines. Since the substrate regions between source and drain is covered between SiO.sub.2 prior to metal deposition and silicidation no silicide is formed in these regions.

Abstract: A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.

Abstract: A method for making a device and the device itself which utilizes selectively doping part of the channel directly adjacent to the source to improve source-channel junction breakdown voltage is disclosed. This is accomplished through reduced dopant incorporation in the channel directly adjacent to the source during the channel doping steps. The portion of the channel which receives less channel dopant should not be so great that the charging of the floating gate is significantly altered.

Abstract: A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. A high quality tunnel oxide is grown on the channel regions of the device, followed by deposition of a polysilicon buffer layer. The use of the polysilicon buffer layer results in short reoxidation beaks. The field oxide is grown in a short, low temperature wet oxidation step, enhanced by the presence of heavy dopant implants. The use of a short, low temperatue oxide growth allows the use of thin nitride masking members and results in short reoxidation beaks as well as less stress on the substrate during field oxide growth. Also, since a low temperature field oxidation is used, the quality of the tunnel oxide will be maintained. The thin nitride masking members are removed in a wet etch process which does not degrade the underlying polysilicon buffer layer.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown without the use of a sacrificial-oxide growth and removal method. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase regon is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: A tungsten silicide reoxidation technique for forming a reoxidation layer in a CMOS device is disclosed. After forming an insulated gate member, which has a silicon-rich tungsten silicide layer overlying a polysilicon layer, it is first oxidized and the oxide is removed to expose WSi for forming a particular source/drain doped device. Then it is annealed in a substantially pure nitrogen ambient for a given time period. A subsequent growth of the reoxidation layer over the gate member by introducing oxygen results in a substantially planarized surface. The combination between tungsten and oxygen is prevented.

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.