Patents by Inventor Been Jon Woo

Been Jon Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simplified dual damascene process
    Patent number: 7015149
    Abstract: A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: March 21, 2006
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventor: Been Jon Woo
  • Simplified dual damascene process
    Publication number: 20050090100
    Abstract: A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).
    Type: Application
    Filed: October 20, 2004
    Publication date: April 28, 2005
    Inventor: Been Jon Woo