Abstract: A method of forming a gate structure is provided. A semiconductor substrate is provided first. A first insulator is formed on the semiconductor substrate. A plurality of dielectric layer structures are formed separate from each other. A portion of the first insulator is exposed. A second insulator is formed on the dielectric layer structure and the exposed first insulator. A portion of the second insulator and the first insulator are removed to form a plurality of spacer structures and to expose the semiconductor substrate. The spacer structures are positioned between the sidewalls of dielectric layer structure, and the exposed semiconductor substrate is positioned between the spacer structures. A third insulator is formed on the exposed semiconductor substrate. A semiconductor layer is formed on the third insulator, wherein the semiconductor layer is positioned between the spacer structures for a conductive gate.

Abstract: A self-aligned silicide process for preventing electrical shorts which is applied on a semiconductor structure. A surface of the semiconductor structure is provided, having a conductive area and an insulation area. A protection structure is formed therebetween by implanting silicon or germanium and depositing a thin layer of titanium, which prevents the formation of native oxide. The device is completed by forming salicide on the conductive area.

Abstract: A processing method for increasing the packaging density of an integrated circuit. The processing method of the present invention includes a gate structure on a semiconductor substrate. An oxide film is formed on adjacent lateral sides of a gate structure. A spacer material is conformally deposited on the oxide film and an oxide portion is formed over the spacer material. The oxide portion has a shape to cover an L-shaped portion of the spacer material. The oxide portion is then removed to expose the L-shaped portion of the spacer material. The gate structures having L-shaped spacers benefit from increased packaging density in an integrated circuit, and improve gap filling and prevent contact-to-gate shorts.