Patents by Inventor Beena Pious
Beena Pious has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9305664Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.Type: GrantFiled: March 26, 2014Date of Patent: April 5, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Stanton Petree Ashburn, Abha Singh Kasper
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Patent number: 9208902Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.Type: GrantFiled: October 29, 2009Date of Patent: December 8, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Xiaowei Deng, Wah Kit Loh, Jon Lescrenier
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Publication number: 20150279487Abstract: An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Applicant: Texas Instruments IncorporatedInventors: Beena Pious, Stanton Petree Ashburn, Abha Singh Kasper
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Patent number: 8693271Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.Type: GrantFiled: February 10, 2012Date of Patent: April 8, 2014Assignee: Texas Instruments IncorporatedInventors: Jayesh C. Raval, Beena Pious, Stanton Petree Ashburn, James Craig Ondrusek
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Patent number: 8542545Abstract: An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.Type: GrantFiled: March 24, 2011Date of Patent: September 24, 2013Assignee: Texas Instruments IncorporatedInventors: Wah Kit Loh, Beena Pious
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Patent number: 8526253Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.Type: GrantFiled: August 29, 2011Date of Patent: September 3, 2013Assignee: Texas Instruments IncorporatedInventors: Beena Pious, Jayesh C. Raval, Wah Kit Loh, Stanton Petree Ashburn
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Publication number: 20130051169Abstract: A method of screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells. A write of the opposite data state is then performed, followed by a read of the memory cells. The process is repeated for the opposite data state.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Beena Pious, Jayesh C. Raval, Wah Kit Loh, Stanton Petree Ashburn
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Publication number: 20130039139Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.Type: ApplicationFiled: February 10, 2012Publication date: February 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jayesh C. Raval, Beena Pious, Stanton Petree Ashburn, James Craig Ondrusek
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Publication number: 20120243354Abstract: An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.Type: ApplicationFiled: March 24, 2011Publication date: September 27, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Wah Kit Loh, Beena Pious
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Publication number: 20100110807Abstract: An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Applicant: Texas Instruments IncorporatedInventors: Beena Pious, Xiaowei Deng, Wah Kit Loh, Jon Lescrenier