Patents by Inventor Behdad Youssefi
Behdad Youssefi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12321713Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.Type: GrantFiled: October 31, 2023Date of Patent: June 3, 2025Assignee: Reconceive AI, Inc.Inventor: Behdad Youssefi
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Publication number: 20240289419Abstract: A compute fabric includes, in part: a multitude of compute tiles disposed in a memory block, a networking circuit coupled to the compute tiles and adapted to enable communication between the compute tiles and further to enable the compute tiles to communicate with a system external to the compute fabric; and controller configured to control the of compute tiles. Each compute tiles includes, in part, a multitude of multiplying bit-cells (MBC) disposed along M rows and N columns, where M an N are integers greater than one. Each MBC is configured to: multiply a first bit by a second bit to generate a multiplication value; convert the multiplication value to a charge; and store the charge in a capacitor disposed in the MBC.Type: ApplicationFiled: February 28, 2024Publication date: August 29, 2024Inventors: Ronald E. Gagnon, JR., Charles Prince Buchbinder, Jorge A. Grilo, Behdad Youssefi
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Publication number: 20240094985Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.Type: ApplicationFiled: October 31, 2023Publication date: March 21, 2024Inventor: Behdad Youssefi
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Patent number: 11842167Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.Type: GrantFiled: November 25, 2020Date of Patent: December 12, 2023Assignee: Areanna Inc.Inventor: Behdad Youssefi
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Publication number: 20210216280Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.Type: ApplicationFiled: November 25, 2020Publication date: July 15, 2021Inventor: Behdad YOUSSEFI
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Patent number: 11055062Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.Type: GrantFiled: February 11, 2019Date of Patent: July 6, 2021Assignee: AREANNA INC.Inventor: Behdad Youssefi
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Patent number: 10417460Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.Type: GrantFiled: September 25, 2018Date of Patent: September 17, 2019Assignee: AREANNA INC.Inventor: Behdad Youssefi
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Patent number: 9024680Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for a capacitor of a stage of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level then subsequently to the auxiliary pump's level.Type: GrantFiled: June 24, 2013Date of Patent: May 5, 2015Assignee: SanDisk Technologies Inc.Inventor: Behdad Youssefi
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Patent number: 8963575Abstract: An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter.Type: GrantFiled: September 26, 2012Date of Patent: February 24, 2015Assignee: SanDisk Technologies Inc.Inventor: Behdad Youssefi
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Patent number: 8941369Abstract: A band-gap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected hand-gap voltage. This allows for the band-gap reference circuit to be trimmed at a single temperature. This allows the circuit to be made with only a single trimmable parameter, which, in the exemplary circuits, is a resistance value.Type: GrantFiled: August 30, 2012Date of Patent: January 27, 2015Assignee: SanDisk Technologies Inc.Inventor: Behdad Youssefi
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Publication number: 20140375378Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for the stages capacitor of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where a the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level than subsequently to the auxiliary pump's level.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventor: Behdad Youssefi
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Publication number: 20140084959Abstract: An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Applicant: SanDisk Technologies Inc.Inventor: Behdad Youssefi
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Patent number: 8542000Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.Type: GrantFiled: November 9, 2012Date of Patent: September 24, 2013Assignee: SanDisk Technologies Inc.Inventor: Behdad Youssefi
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Publication number: 20130241522Abstract: A band-gap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected hand-gap voltage. This allows for the band-gap reference circuit to be trimmed at a single temperature. This allows the circuit to be made with only a single trimmable parameter, which, in the exemplary circuits, is a resistance value.Type: ApplicationFiled: August 30, 2012Publication date: September 19, 2013Inventor: Behdad Youssefi
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Publication number: 20130241523Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.Type: ApplicationFiled: November 9, 2012Publication date: September 19, 2013Applicant: SanDisk Technologies Inc.Inventor: Behdad Youssefi