Patents by Inventor Behdad Youssefi

Behdad Youssefi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12321713
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: June 3, 2025
    Assignee: Reconceive AI, Inc.
    Inventor: Behdad Youssefi
  • Publication number: 20240289419
    Abstract: A compute fabric includes, in part: a multitude of compute tiles disposed in a memory block, a networking circuit coupled to the compute tiles and adapted to enable communication between the compute tiles and further to enable the compute tiles to communicate with a system external to the compute fabric; and controller configured to control the of compute tiles. Each compute tiles includes, in part, a multitude of multiplying bit-cells (MBC) disposed along M rows and N columns, where M an N are integers greater than one. Each MBC is configured to: multiply a first bit by a second bit to generate a multiplication value; convert the multiplication value to a charge; and store the charge in a capacitor disposed in the MBC.
    Type: Application
    Filed: February 28, 2024
    Publication date: August 29, 2024
    Inventors: Ronald E. Gagnon, JR., Charles Prince Buchbinder, Jorge A. Grilo, Behdad Youssefi
  • Publication number: 20240094985
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 21, 2024
    Inventor: Behdad Youssefi
  • Patent number: 11842167
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 12, 2023
    Assignee: Areanna Inc.
    Inventor: Behdad Youssefi
  • Publication number: 20210216280
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
    Type: Application
    Filed: November 25, 2020
    Publication date: July 15, 2021
    Inventor: Behdad YOUSSEFI
  • Patent number: 11055062
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: July 6, 2021
    Assignee: AREANNA INC.
    Inventor: Behdad Youssefi
  • Patent number: 10417460
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 17, 2019
    Assignee: AREANNA INC.
    Inventor: Behdad Youssefi
  • Patent number: 9024680
    Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for a capacitor of a stage of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level then subsequently to the auxiliary pump's level.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 5, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi
  • Patent number: 8963575
    Abstract: An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi
  • Patent number: 8941369
    Abstract: A band-gap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected hand-gap voltage. This allows for the band-gap reference circuit to be trimmed at a single temperature. This allows the circuit to be made with only a single trimmable parameter, which, in the exemplary circuits, is a resistance value.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 27, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi
  • Publication number: 20140375378
    Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for the stages capacitor of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where a the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level than subsequently to the auxiliary pump's level.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventor: Behdad Youssefi
  • Publication number: 20140084959
    Abstract: An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi
  • Patent number: 8542000
    Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 24, 2013
    Assignee: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi
  • Publication number: 20130241522
    Abstract: A band-gap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected hand-gap voltage. This allows for the band-gap reference circuit to be trimmed at a single temperature. This allows the circuit to be made with only a single trimmable parameter, which, in the exemplary circuits, is a resistance value.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 19, 2013
    Inventor: Behdad Youssefi
  • Publication number: 20130241523
    Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.
    Type: Application
    Filed: November 9, 2012
    Publication date: September 19, 2013
    Applicant: SanDisk Technologies Inc.
    Inventor: Behdad Youssefi