Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication.

Abstract: An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.

Abstract: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.

Abstract: An extendable timing architecture for an integrated circuit is disclosed. The extendable timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.

Abstract: A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to a contact layer so that a user can customize and program different blocks of the SMPW to the user's requirements. An SMPW provider maintains an inventory of SMPWs. If one of the SMPWs can meet all of a user's IC design requirements, or can serve an intermediate step in a user's IC design process, such as market/concept validation or IP validation, the SMPW is provided to the user. The user can then proceed directly to production using a streamlined design flow having a very short cycle time of 1–3 months. Otherwise, the user proceeds to production using a normal design flow having a much longer cycle time.

Abstract: A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to a contact layer so that a user can customize and program different blocks of the SMPW to the user's requirements. An SMPW provider maintains an inventory of SMPWs. If one of the SMPWs can meet all of a user's IC design requirements, or can serve an intermediate step in a user's IC design process, such as market/concept validation or IP validation, the SMPW is provided to the user. The user can then proceed directly to production using a streamlined design flow having a very short cycle time of 1-3 months. Otherwise, the user proceeds to production using a normal design flow having a much longer cycle time.