Abstract: A technique for at-speed testing of the core logic of a digital integrated circuit device is disclosed. Test patterns are applied to the circuit inputs while applying a "burst" of three clock pulses followed by a "dead cycle"to the pipeline stages between the input logic, the core logic and the output logic. During the dead cycle, changes in the outputs of the device are observed during the dead cycle. Subsequently, a second burst of clock pulses, offset from the first burst, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. Subsequently, a third burst of clock pulses, offset from the first and second bursts, and followed by a dead cycle, is applied with re-initialized test patterns, and the outputs are observed during the dead cycle. The results of the three iterations of the test are stored and merged to provide a valid indication of the performance of the device with a free running clock.