Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the lead frame proximate to a geometric center of the lead frame may be rounded to include a radius of curvature of at least two times a greatest thickness of the die-attach pad. The thickness of the die-attach pad may be measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and each one of the lead fingers having a surface area larger than an average surface area of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the lead frame proximate to a geometric center of the lead frame may be rounded to include a radius of curvature of at least two times a greatest thickness of the die-attach pad. The thickness of the die-attach pad may be measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and each one of the lead fingers having a surface area larger than an average surface area of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.

Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.

Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.

Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: The present disclosure describes an embodiment of an apparatus comprising a first dielectric layer having a first variation of capacitance with temperature, a second dielectric layer having a second variation of capacitance with temperature, the second variation of capacitance with temperature being different than the first variation of capacitance with temperature, and a conductive layer sandwiched between the first and second dielectric layers. Also described is an embodiment of a process comprising forming a first dielectric layer comprising a dielectric having a first composition, stacking a conductive layer on the first dielectric layer, and stacking a second dielectric layer on the conductive layer, the second dielectric layer having a second composition different than the first composition. Other embodiments are also described and claimed.

Abstract: A method and apparatus is provided that pertains to a low inductance capacitor. The capacitor has a first surface electrically interconnected to a plurality of conductive electrodes and one or more second surfaces electrically interconnected to a plurality of electrodes interposed between the electrodes electrically interconnected to the first conductive surface. A dielectric layer separates the layered plurality of electrodes. The one or more second conductive surfaces are positioned within the body of the layered electrodes, such that the distance between the terminations of the first conductive surface and the one or more second conductive surfaces is shortened to lower inductance.

Abstract: A method and apparatus is provided that pertains to a low inductance capacitor. The capacitor has a first surface electrically interconnected to a plurality of conductive electrodes and one or more second surfaces electrically interconnected to a plurality of electrodes interposed between the electrodes electrically interconnected to the first conductive surface. A dielectric layer separates the layered plurality of electrodes. The one or more second conductive surfaces are positioned within the body of the layered electrodes, such that the distance between the terminations of the first conductive surface and the one or more second conductive surfaces is shortened to lower inductance.

Abstract: A ball grid array integrated circuit package which has a plurality of elliptical shaped solder pads located on a substrate of the package. Routing traces are connected to the apexes of the elliptical shaped solder pads. Connecting a routing trace to the apex of an elliptical shaped solder pad reduces the stress points on the trace/pad interface. Vias may be coupled to the solder pads and the routing traces. The vias are located at the apexes of the elliptical shaped solder pads to reduce the stress points of the substrate.

Abstract: An electronics package includes a substrate, a via and a solder ball. The substrate has first and second opposed surfaces. The via is located within the substrate and terminates at the first surface. The via defines an opening having first and second opposed walls. The solder ball is at least partially located over the opening. The solder ball has first and second opposed sides, the first side being adjacent the first wall and the second side being adjacent the second wall. The first side is nearer to the first wall than the second side is to the second wall.

Abstract: A heat sink incorporated into an electronic package. The package contains an integrated circuit enclosed by a dielectric housing. Coupled to the circuit is a lead frame which has a plurality of leads that extend from the outer edges of the housing. The heat sink has a bottom surface pressed against the lead frame and an opposite top surface that is exposed to the ambient. The heat sink also has a pair of oblique steps which engage the housing and insure that the sink does not become detached from the package.

Abstract: An integrated circuit package that contains a heat spreader which has a plurality of legs stamped from a sheet of metal material. The heat spreader also has a plurality of slots which allow plastic to flow between the bonding wires of the integrated circuit assembly during the molded injection process of the package.

Abstract: A heat sink incorporated into an electronic package. The package contains an integrated circuit enclosed by a dielectric housing. Coupled to the circuit is a lead frame which has a plurality of leads that extend from the outer edges of the housing. The heat sink has a bottom surface pressed against the lead frame and an opposite top surface that is exposed to the ambient. The heat sink also has a pair of oblique steps which engage the housing and insure that the sink does not become detached from the package.