Abstract: A power conversion circuit, such as a buck converter/regulator, includes a feedback loop operatively coupling the output voltage to the controller for the switching mechanism. The feedback loop includes an analog error amplifier that sources current to the controller when the output voltage falls below a predetermined reference voltage and sinks current from the controller when the output voltage rises above a predetermined reference voltage. The feedback loop further includes at least one of a sinking boost circuit that sinks additional current from the controller when the output voltage falls below a low voltage threshold or a sourcing boost circuit that sources additional current to the controller when the output voltage rises above a high voltage threshold. The boost circuits can include analog amplifiers, digital comparators, or a combination thereof.

Abstract: This disclosure relates to power converters that are capable of providing smooth transitions between multiple output voltage levels. The converter's output may need to be changed from, e.g., 5V to 12V, 15V, or 20V—based on the charging device's request. By using improved power converter designs comprising both a flyback converter circuit and variable-frequency buck converter circuit that may each be selectively coupled to an output load, a more smooth, e.g., monotonous, transition between output voltage levels may be achieved. In particular, by varying the switching frequency of the buck converter in a controlled way, the output voltage of the power converter may rise monotonically during the transition between output voltage levels. According to some embodiments, once the output of the buck converter has reached its maximum value, the buck converter may be disabled, and the flyback converter may be enabled to begin supplying the output voltage to the load.

Abstract: This application relates to systems, methods, and apparatus for controlling a switching frequency of a boost or flyback converter to be above an audible frequency range when operating the boost or flyback converter in a pulse frequency modulation (PFM) mode. The boost or flyback converter uses one or more switches for converting power for a display panel. In order to boost the switching frequency when operating in the PFM mode, the boost or flyback converter can selectively implement certain current and/or voltage limits for pulses that are generated as a result of the switching. The current and/or voltage limits can be set according to a load of the boost or flyback converter, and a correspondence between the current and/or voltage limits and the loads can be stored in a lookup table accessible to the boost or flyback converter.

Abstract: Various systems and methods are disclosed herein, which provide isolated systems with an auxiliary, multi-signal digital feedback loop for reporting a plurality of different potential fault conditions in an output system (e.g., output short circuit, output over-voltage, output under-voltage, output over temperature, etc.) to a Primary Controller in an input system. The signals may be sent according to any desired standardized (or proprietary) data transmission protocols. Use of a digital feedback loop allows the signals to be passed to the Primary Controller more quickly than is allowed by traditional analog feedback paths—and while using only a single optocoupler device for the transmission of all fault conditions. The techniques disclosed herein are applicable to any number of isolated systems that supply power to electronic systems such as: digital cameras, mobile phones, watches, personal data assistants (PDAs), portable music players, monitors, as well as desktop, laptop, and tablet computers.

Abstract: Various systems, apparatuses, and methods are disclosed herein, which provide a new power conversion topology for isolated systems that does not include a transformer. Embodiments of the inventive systems comprise: a switching system utilizing high voltage, low leakage switches, e.g., Silicon Carbide (SiC) MOS-FETs; a power source; an inductor and a capacitor operating as a link stage resonant LC circuit; and a load. The switching system may be configured to be controlled in a synchronized ‘four phase’ control loop process, wherein the input switches are prevented from being closed at the same time as the output switches, thereby providing electrical isolation between the input power source and the load—without the use of a transformer. The techniques disclosed herein are applicable to any number of isolated systems that supply power to electronic systems such as: digital cameras, mobile phones, watches, personal data assistants (PDAs), portable music players, displays, and computers.

Abstract: A power conversion circuit, such as a buck converter/regulator, includes a feedback loop operatively coupling the output voltage to the controller for the switching mechanism. The feedback loop includes an analog error amplifier that sources current to the controller when the output voltage falls below a predetermined reference voltage and sinks current from the controller when the output voltage rises above a predetermined reference voltage. The feedback loop further includes at least one of a sinking boost circuit that sinks additional current from the controller when the output voltage falls below a low voltage threshold or a sourcing boost circuit that sources additional current to the controller when the output voltage rises above a high voltage threshold. The boost circuits can include analog amplifiers, digital comparators, or a combination thereof.

Abstract: The embodiments discussed herein relate to systems, methods, and apparatus for executing a pulse frequency modulation (PFM) mode of a boost converter in order to ensure that a switching frequency of the boost converter is a above an audible frequency threshold. In this way, a user operating a display device that is controlled by the boost converter will not be disturbed by audible noises generated at the display device. The PFM mode enforces an audible frequency threshold by using control circuitry designed to increase or decrease the frequency of a pulse signal depending on how the frequency of the pulse signal changes over time. The control circuitry can apply an additional load to the boost converter in order to increase the frequency of the pulse signal when the frequency is approaching the audible frequency threshold.

Abstract: The embodiments discussed herein relate to systems, methods, and apparatus for executing a pulse frequency modulation (PFM) mode of a boost converter in order to ensure that a switching frequency of the boost converter is a above an audible frequency threshold. In this way, a user operating a display device that is controlled by the boost converter will not be disturbed by audible noises generated at the display device. The PFM mode enforces an audible frequency threshold by using control circuitry designed to increase or decrease the frequency of a pulse signal depending on how the frequency of the pulse signal changes over time. The control circuitry can apply an additional load to the boost converter in order to increase the frequency of the pulse signal when the frequency is approaching the audible frequency threshold.

Abstract: A method for generating an oscillator signal uses a multiphase oscillator having a plurality of input stages and a reference stage. Each input stage produces an input stage voltage that represents a phase for the oscillator. The input stage voltages produced by each of the input stages are compared to a reference voltage produced by the reference stage. An input stage having a maximum input stage voltage is selected and an output of the selected input stage having the maximum input stage voltage is changed. A current need of the oscillator is detected with a negative feedback loop coupled to the reference stage. An appropriate supply current is provided to each input stage with the negative feedback loop.

Abstract: A method for generating an oscillator signal uses a multiphase oscillator having a plurality of input stages and a reference stage. Each input stage produces an input stage voltage that represents a phase for the oscillator. The input stage voltages produced by each of the input stages are compared to a reference voltage produced by the reference stage. An input stage having a maximum input stage voltage is selected and an output of the selected input stage having the maximum input stage voltage is changed. A current need of the oscillator is detected with a negative feedback loop coupled to the reference stage. An appropriate supply current is provided to each input stage with the negative feedback loop.

Abstract: A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmtnx for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx thus its process and environmental variation.

Abstract: An oscillator includes a reference stage and multiple phase stages. The reference stage has a reference transistor having a gate coupled to a voltage reference and a drain coupled to a reference current source. Each phase stage includes a transistor, two current sources, a capacitor, switch, inverter, and latch. The transistor has a drain coupled to a first current source, a gate coupled to a node and a source coupled to the reference transistor's source. The capacitor and switch couple between the node and ground. The second current source couples to the node. The transistor's drain couples to the inverter's input. The inverter's output couples to the latch's set input. The latch's output couples to the switch. The inverter output also couples to the reset input of a subsequent phase stage's latch. The inverter output for a last stage couples to the reset input of a first stage latch.

Abstract: A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.

Abstract: A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.

Abstract: A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window Vhys. The hysteretic comparator includes a differential input stage with current output (DICO) having input transistors with transconductance Gmin, for converting the input signals, with an input stage transconductance Gmin, into intermediate signal currents. A steerable offset current generator, driven by a steering control signal, steers an offset current source IOS to alternative offset currents. A current-to-voltage summing converter (IVSC) sums up the intermediate signal currents and the offset currents and converts the result into VOT plus the steering control signal causing Vhys=IOS/Gmin. A feedback resistance RNF is connected to the input transistors to form a negative feedback loop. The RNF is sized such that GMin, hence Vhys, becomes essentially solely dependent upon the feedback conductance GNF=1/RNF independent of the Gmtnx, thus its process and environmental variation.

Abstract: An oscillator includes a reference stage and multiple phase stages. The reference stage has a reference transistor having a gate coupled to a voltage reference and a drain coupled to a reference current source. Each phase stage includes a transistor, two current sources, a capacitor, switch, inverter, and latch. The transistor has a drain coupled to a first current source, a gate coupled to a node and a source coupled to the reference transistor's source. The capacitor and switch couple between the node and ground. The second current source couples to the node. The transistor's drain couples to the inverter's input. The inverter's output couples to the latch's set input. The latch's output couples to the switch. The inverter output also couples to the reset input of a subsequent phase stage's latch. The inverter output for a last stage couples to the reset input of a first stage latch.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.