Patents by Inventor Behzad R. Sayyah

Behzad R. Sayyah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9197892
    Abstract: A system (and a method) are disclosed for intelligently fetch one or multiple reference blocks from memory for each block to be motion compensated or motion estimated within a video processing system. The system includes a reference block configuration evaluation unit and a motion compensation memory fetching unit. The reference block configuration evaluation unit analyzes the reference block configuration of the block being motion compensated with a plurality of reference block configurations of its neighboring blocks. In response to a reference block configuration evaluation result, the reference block configuration evaluation unit decides the configuration of reference blocks to be fetched from a memory. The motion vector memory fetching unit fetches the number of reference blocks for motion compensation accordingly.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jacob Rojit, Alexander Naum Kipnis, Behzad R. Sayyah
  • Patent number: 9083976
    Abstract: A system (and a method) are disclosed for a video processing system with enhanced entropy coding performance. The system includes an entropy decoder configured to divide decoding of an input video stream into arithmetic decoding and syntax decoding. The entropy decoder includes an arithmetic decoding module, a syntax decoding module, a memory management module and a memory buffer connecting the two decoding modules. The arithmetic decoding module is configured to decode the input video stream into multiple bins of decoded input video stream and the syntax decoding module is configured to decode the bins of arithmetically decoded input videos stream into one or more syntax elements. The memory management module uses the memory buffer to accelerate the coding performances of arithmetic decoding and syntax decoding. The system also includes a corresponding entropy encoder configured to encode a video stream with improved coding performance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 14, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jun Xin, Behzad R. Sayyah, William Ka-ming Chan
  • Patent number: 8767838
    Abstract: A system (and a method) are disclosed for a video processing system cascading multiple transcoders. The system includes a first transcoder, a second transcoder and an optional third transcoder. The first transcoder is a pre-processing transcoder configured to preprocess an input video stream into a first bitstream in a first video format. The second transcoder is a primary transcoder configured to transcode the first bitstream into a second bitstream in a second video format. The third transcoder comprises a post-processing transcoder configured to further transcode the second bitstream into a third bitstream in a third video format. Pre-processing and post-processing the input video stream by the cascaded transcoders allows the system to more efficiently and quickly transcode the input video stream. Pre-processing and post-processing the input video further improves processing efficiency and speed and also increases throughout of coding processing.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 1, 2014
    Assignee: Zenverge, Inc.
    Inventors: Jun Xin, Behzad R. Sayyah, William K. Chan
  • Patent number: 8411749
    Abstract: A system (and a method) are disclosed for intelligently fetch one or multiple reference blocks from memory for each block to be motion compensated or motion estimated within a video processing system. The system includes a reference block configuration evaluation unit and a motion compensation memory fetching unit. The reference block configuration evaluation unit analyzes the reference block configuration of the block being motion compensated with a plurality of reference block configurations of its neighboring blocks. In response to a reference block configuration evaluation result, the reference block configuration evaluation unit decides the configuration of reference blocks to be fetched from a memory. The motion vector memory fetching unit fetches the number of reference blocks for motion compensation accordingly.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: April 2, 2013
    Assignee: Zenverge, Inc.
    Inventors: Rojit Jacob, Alexander Kipnis, Behzad R. Sayyah