Abstract: A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.

Abstract: A circuit including: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to detecting the current pulse on its input, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier detects the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain feeding back to the reset terminal of the resettable amplifier a feedback signal derived from the output signal of the resettable amplifier.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 ?m CMOS technology.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: The present invention describes a transmitter/receiver architecture that uses a Weaver architecture in conjunction with digitally controlled adder/subtractor components to insert/extract a signal into/from the multi-channel system. In the transmitter, the selection of the band select bit causes the up/downconverted IF baseband I and Q signals to insert/extract on either side of an RF LO signal. In addition, the image of the first LO is eliminated while the desired signal is enhanced after passing through this new architecture. The invention also adds an RSSI circuit to the MBOA Weaver architecture receiver architecture to detect whether an 802.11 WLAN signal is interfering with the desired UWB signal. If so, the system is designed to detect this interference and jump to a new frequency range to avoid this interference. This invention focuses on devices that operate over the entire UWB band including the newly formed 60 GHz UWB band system.

Abstract: The present invention provides reduces the number of required synthesizers thereby reducing the area and power concerns to extract/insert a signal from/to a multi-channel communication system and is also known as frequency planning. The highest frequency of operation required for the synthesizers or oscillators is approximately the midpoint of the entire signal frequency range. Two superimposed Weaver architectures are used to form the architecture. The receiver extracts the baseband I and Q signals from the multi-channel communication system, while the transmitter upconverts the baseband I and Q signals to the multi-channel communication system. The Weaver architecture, depending on the select bit, can enhance the image signal and reduce the desired signal or the image signal can be reduced while the desired signal is enhanced. Because the image and signal components are symmetrically displaced from the RF LO, less IF LO frequencies or synthesizers are required to operate the system.

Abstract: A high-speed latch includes a latch unit and a first current source. The latch unit has a first input terminal for receiving a first input signal and a first output terminal for outputting a first output signal. The first current source is coupled to the first output terminal, and is enabled for providing the first output terminal with a first driving current to reduce a voltage difference between the first output signal and the first input signal when the first output signal and the first input signal correspond to different logic states.

Abstract: A circuit including: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to detecting the current pulse on its input, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier detects the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain feeding back to the reset terminal of the resettable amplifier a feedback signal derived from the output signal of the resettable amplifier.

Abstract: A low noise amplifier (LNA) for filtering an input signal to generate an output signal. The low noise amplifier includes a switched loading circuit having a plurality of loading units, each of the loading units determining a corresponding center frequency of the low noise amplifier. The switched loading circuit selectively enables a loading unit having the desired corresponding center frequency. At least one converters coupled to the switched loading circuit converts a voltage of the input signal into a loading current and passes the loading current through the enabled loading unit to generate the output signal.

Abstract: A high-speed latch includes a latch unit and a first current source. The latch unit has a first input terminal for receiving a first input signal and a first output terminal for outputting a first output signal. The first current source is coupled to the first output terminal, and is enabled for providing the first output terminal with a first driving current to reduce a voltage difference between the first output signal and the first input signal when the first output signal and the first input signal correspond to different logic states.

Abstract: A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.

Abstract: A low noise amplifier (LNA) for filtering an input signal to generate an output signal. The low noise amplifier includes a switched loading circuit having a plurality of loading units, each of the loading units determining a corresponding center frequency of the low noise amplifier. The switched loading circuit selectively enables a loading unit having the desired corresponding center frequency. At least one converters coupled to the switched loading circuit converts a voltage of the input signal into a loading current and passes the loading current through the enabled loading unit to generate the output signal.

Abstract: A mixer circuit of the present invention includes a gain stage configured to receive a first signal and a modulated bias current, and in accordance therewith, produce an output signal, the gain stage generating a first current and receiving the modulated bias current from a bias circuit on a common node. The bias circuit includes an input configured to receive a second signal, and in accordance therewith, generate the modulated bias current. The mixer circuit also includes a current shunt circuit for generating a second current. The first current, the second current, and the modulated bias current are coupled to the common node. In one embodiment, the first signal is approximately a square wave, and the frequency of the first signal is one-third the frequency of the second signal.

Abstract: A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.

Abstract: A local oscillator architecture provides a signal at an output frequency with reduced pulling effect. A voltage controlled oscillator (VCO) generates a first signal having a frequency that is a fraction of the output frequency. A frequency shifter generates a second signal with a frequency substantially equal to the difference between the VCO frequency and the output frequency. Single-sideband mixers are used to produce output signals at the sum of the VCO frequency and the shifted frequency while suppressing an unwanted sideband at the difference of the two frequencies.

Abstract: In accordance with embodiments of the present invention, a receiver system is provided with a variable gain mixer circuit that is advantageous over current architectures used in wireless communication systems. The use of a variable gain mixer circuit simplifies the receiver architecture resulting in the elimination of additional circuit blocks and a reduction in complexity and cost. Moreover, one embodiment of the present invention includes a mixer circuit comprising a mixer core, a bias circuit coupled to the mixer core for providing a bias current, and a variable impedance network. The mixer core receives input signals and generates output currents that are coupled to the variable impedance network. Each of the output currents are selectively coupled to a voltage output node through a variable impedance. Variable gain is established by varying the impedance between the output currents of the mixer core and the voltage output node.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 &mgr;m CMOS technology.

Abstract: In accordance with the present invention a mixer circuit noise reduction technique is provided. The mixer circuit of the present invention includes a gain stage for receiving a first signal and producing an output signal. The mixer circuit also includes a bias circuit coupled to the gain stage through a common node for providing a bias current to the gain stage, the bias circuit having an input for receiving a second signal, and in accordance therewith, varying the bias current. Additionally, the mixer circuit includes a frequency dependent current shunt circuit coupled between the common node and a reference voltage, wherein a first portion of the bias current frequency components within a first frequency range are coupled to the reference voltage by the shunt circuit, and a second portion of the bias current frequency components within a second frequency range are coupled to the reference voltage by the shunt circuit, the first portion being larger than the second portion.

Abstract: A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.