Patents by Inventor Bei Zhu
Bei Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10941033Abstract: A method includes fusion bonding a first side of a MEMS wafer to a second side of a first handle wafer. A TSV is formed from a first side of the first handle wafer to the second side of the first handle wafer and into the first MEMS wafer. A dielectric layer is formed on the first side of the first handle wafer. A tungsten via is formed in the dielectric layer. Electrodes are formed on the dielectric layer. A second MEMS wafer is eutecticly bonded with a first eutectic bond to the electrodes, wherein the TSV electrically connects the first MEMS wafer to the second MEMS wafer. Standoffs are formed on a second side of the first MEMS wafer. A CMOS wafer is eutecticly bonded with a second eutectic bond to the standoffs, wherein the second eutectic bond includes different materials than the first eutectic bond.Type: GrantFiled: August 14, 2019Date of Patent: March 9, 2021Assignee: InvenSense, Inc.Inventors: Dongyang Kang, Bongsang Kim, Bei Zhu, Ian Flader
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Publication number: 20200131027Abstract: A method includes fusion bonding a first side of a MEMS wafer to a second side of a first handle wafer. A TSV is formed from a first side of the first handle wafer to the second side of the first handle wafer and into the first MEMS wafer. A dielectric layer is formed on the first side of the first handle wafer. A tungsten via is formed in the dielectric layer. Electrodes are formed on the dielectric layer. A second MEMS wafer is eutecticly bonded with a first eutectic bond to the electrodes, wherein the TSV electrically connects the first MEMS wafer to the second MEMS wafer. Standoffs are formed on a second side of the first MEMS wafer. A CMOS wafer is eutecticly bonded with a second eutectic bond to the standoffs, wherein the second eutectic bond includes different materials than the first eutectic bond.Type: ApplicationFiled: August 14, 2019Publication date: April 30, 2020Inventors: Dongyang KANG, Bongsang KIM, Bei ZHU, Ian FLADER
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Patent number: 8551831Abstract: An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region.Type: GrantFiled: September 19, 2008Date of Patent: October 8, 2013Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Da Wei Gao, Bei Zhu, Hanming Wu, John Chen, Paolo Bonfanti
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Patent number: 8350253Abstract: An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.Type: GrantFiled: January 29, 2010Date of Patent: January 8, 2013Assignee: Xilinx, Inc.Inventors: Bei Zhu, Hong-Tze Pan, Bang-Thu Nguyen, Qi Lin, Zhiyuan Wu, Ping-Chin Yeh, Jae-Gyung Ahn, Yun Wu
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Patent number: 8299564Abstract: Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.Type: GrantFiled: September 14, 2009Date of Patent: October 30, 2012Assignee: Xilinx, Inc.Inventors: Yun Wu, Bei Zhu, Zhiyuan Wu, Michael J. Hart
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Patent number: 8058120Abstract: A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions.Type: GrantFiled: July 28, 2010Date of Patent: November 15, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xian Jie Ning, Bei Zhu
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Publication number: 20110070701Abstract: A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions.Type: ApplicationFiled: July 28, 2010Publication date: March 24, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xian Jie Ning, Bei Zhu
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Patent number: 7557000Abstract: A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure.Type: GrantFiled: December 12, 2006Date of Patent: July 7, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: John Chen, Hanming Wu, Da Wei Gao, Bei Zhu, Paolo Bonfanti
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Publication number: 20090152599Abstract: An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region.Type: ApplicationFiled: September 19, 2008Publication date: June 18, 2009Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Da Wei Gao, Bei Zhu, Hanming Wu, John Chen, Paolo Bonfanti
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Publication number: 20080173941Abstract: A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.Type: ApplicationFiled: February 24, 2007Publication date: July 24, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Bei Zhu, Paolo Bonfanti, Hanming Wu, Da Wei Gao, John Chen
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Publication number: 20080119032Abstract: A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure.Type: ApplicationFiled: December 12, 2006Publication date: May 22, 2008Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: John Chen, Hanming Wu, Da Wei Gao, Bei Zhu, Paolo Bonfanti
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Patent number: 7335566Abstract: A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the drain region free from the dopant impurities.Type: GrantFiled: October 10, 2006Date of Patent: February 26, 2008Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xian J. Ning, Bei Zhu
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Publication number: 20070196992Abstract: A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate layer (e.g., polysilicon) overlying the dielectric layer. The method patterns the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. In a specific embodiment, sidewall spacers are formed using portions of the dielectric layer. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer.Type: ApplicationFiled: May 26, 2006Publication date: August 23, 2007Applicant: Semiconductor Manufacturing Int'l (Shanghai) CorporationInventors: Mo Hong Xiang, John Chen, Bei Zhu, Dai Gao, Hanming Wu
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Publication number: 20070184668Abstract: A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the gate region free from the dopant impurities.Type: ApplicationFiled: October 10, 2006Publication date: August 9, 2007Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xian Ning, Bei Zhu