Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: A semiconductor device includes a first channel structure extending in a first direction in a stack structure, a conductive layer extending in a second direction perpendicular to the first direction and surrounding at least partial of the first channel structure, a first isolation structure extending in the first direction and the second direction, and a second isolation structure extending in the first direction and the second direction. The first channel structure and the conductive layer are disposed between the first isolation structure and the second isolation structure, and a first distance between the first channel structure and the first isolation structure is less than a second distance between the first channel structure and the second isolation structure.

Abstract: Embodiments of the present disclosure provide method and apparatus for P-CSCF restoration. A method performed by a session management node comprises receiving a message from a data management node or a policy control node or a first access and mobility node. The message indicates proxy call session control function (P-CSCF) restoration and information of a failed P-CSCF. The method further comprises, for a protocol data unit (PDU) session, based on the received message, triggering a P-CSCF restoration procedure by sending a PDU session release command or a PDU session modification command to a user equipment via the first or a second access and mobility node. The PDU session modification command comprises an updated P-CSCF list based on the information of the failed P-CSCF.

Abstract: Semiconductor devices, methods for forming such semiconductor devices, and systems including such semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a stack structure and a transistor. The stack structure includes first conductive layers and second conductive layers that are stacked alternately in a first direction. The transistor is disposed on one side of the stack structure and connected with one of the first conductive layers. The first semiconductor structure further includes a first connection structure extending through the stack structure in the first direction and connected to the second conductive layers.

Abstract: A semiconductor device includes a first gate structure and a second gate structure extending in a first direction and a second direction, a first isolation structure deposited between the first gate structure and the second gate structure extending in the first direction and the second direction, a first semiconductor structure deposited between the first gate structure and the first isolation structure extending in the first direction, a first contact structure deposited on the first semiconductor structure, a first dielectric layer deposited on the first gate structure, and a second dielectric layer deposited on the first isolation structure. A first center of the first end of the first contact structure in a third direction is perpendicular to the first direction. The second direction aligns with a second center of the first semiconductor structure in the third direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device is a memory device and comprises an array of memory cells in an array region, word lines extending parallel in a first lateral direction, bit lines extending parallel in a second lateral direction different from the first lateral direction, and interconnection structures located within the array region and coupled with the bit lines, and arranged in staggered rows along the first lateral direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device is a memory device and comprises an array of memory cells in an array region, word lines extending parallel in a first lateral direction, bit lines extending parallel in a second lateral direction, and interconnection structures located within the array region and coupled with the word lines, and arranged in staggered columns along the second lateral direction.

Abstract: Examples of the present disclosure provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes semiconductor pillars arranged along a first direction and a second direction, wherein the first direction intersects the second direction; gate lines spaced apart along the first direction, wherein each of the gate lines extends along the second direction and is connected with the semiconductor pillars arranged along the second direction; a first cavity between two adjacent gate lines along the first direction and extending along the second direction; bit lines spaced apart along the second direction, wherein each of the bit lines extends along the first direction and is connected with the semiconductor pillars arranged along the first direction; and a second cavity between two adjacent bit lines along the second direction and extending along the first direction, wherein the second cavity and the first cavity are connected.

Abstract: Memory devices and fabricating methods thereof are disclosed. In some implementations, the disclose memory device comprises a capacitor stack structure and an array of transistors. The capacitor stack structure comprises first electrode plates and second electrode plates alternatively stacked along a vertical direction, a common electrode vertically extending through the capacitor stack structure and in contact with the first electrode plates, and select electrodes each extending through the capacitor stack structure and in contact with a corresponding one of the second electrode plates. Each transistor of the array of transistors is coupled with a corresponding one of the select electrodes.

Abstract: An electrochemical apparatus includes a housing, an electrode assembly, and a first conductive plate. The housing includes a main body portion and a sealing structure. The main body portion includes a first end wall and a second end wall opposite to each other in a first direction, a first wall and a second wall opposite to each other in a second direction, and a first side wall and a second side wall opposite to each other in a third direction. The sealing structure includes a first sealing portion connected to the first end wall and a second sealing portion connected to the first side wall. The first sealing portion folds in a direction towards the first wall. The first conductive plate includes a first surface facing the first wall and a second surface facing the second wall. An insulation adhesive connects the first conductive plate and the first sealing portion.

Abstract: Embodiments of the present disclosure provide method and apparatus for session management. A method performed by a first session management node comprises receiving a deregistration notification of a protocol data unit (PDU) session of a user equipment from a data management node. The deregistration notification comprises a deregistration reason indicating duplicated PDU session. The method further comprises releasing at least one resource corresponding to the PDU session.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: Disclosed herein is a memory device that includes a stack structure. The stack structure has alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: A method for identifying an individual of an oplegnathus punctatus based on a convolutional neural network is provided. Target initial positioning involves three continuous convolutional layers and an average pooling layer. A region of feature interest point is obtained, a hyperparameter candidate box is set to obtain a region, thereby obtaining an approximate position of a target object. II_Net backbone convolutional neural network includes six convolutional layers and four pooling layers, which includes a LeakyReLU activation function used as an activation function of the first convolutional layer, convolutional network layers of Alexnet and parameter data, and a maximum pooling layer of an overlapped pooling structure. Fully connected layers use a genetic algorithm to improve data transmission between layers. With the established model, identification of the individual of the oplegnathus punctatus is performed by using test data.

Abstract: A semiconductor device includes N number of decks. Each deck includes alternating word line layers and insulating layers. Each deck includes two first gate line slit (GLS) structures and a second GLS structure positioned between the two first GLS structures. The two first GLS structures and the second GLS structures each extend in an X-Z plane and cut through the word line layers and the insulating layers of the respective deck. At least one second GLS structure of at least one deck in the N umber of decks includes multiple sub-GLS structures. The multiple sub-GLS structures are separate from each other.

Abstract: A semiconductor device includes decks stacked over a semiconductor layer in a vertical direction. Each deck includes alternating word line layers and insulating layers. A gate line structure (GLS) extends through the word line layers and the insulating layers of the decks. A channel structure extends through the word line layers and the insulating layers of the decks. A sidewall of the GLS is discontinuous at a border between two neighboring decks, and a sidewall of the channel structure is discontinuous at an interface between two neighboring decks. The GLS includes a first GLS that includes a gate line slit, a second GLS that includes sub-GLSs spaced apart from each other in a horizontal direction, or a combination thereof.