Abstract: A utility management system and method including a water collection apparatus; a water storage apparatus in fluid communication with the water collection apparatus; a water storage quantity sensor; one or more water usage sensors; an energy generation apparatus; an energy storage apparatus coupled to the energy generation apparatus; an energy storage quantity sensor; one or more energy usage sensors; a processor with one or more channels to receive at least weather forecast data, water usage data, and energy usage data, and one or more channels to send at least a request for weather forecast data, wherein the processor is coupled to the one or more water usage sensors and energy usage sensors, and wherein the processor is programmed to use the received data to project water collection, water storage, energy generation, and energy storage and to formulate recommendations for water and energy usage; a control interface; and a data display.

Abstract: A unified control scheme to achieve seamless mode change between grid-connected mode and islanded mode for photovoltaic (PV) systems includes two decoupled control units: a DC-DC converter control unit and a DC-AC converter control unit. The DC-bus voltage is controlled through the DC-DC converter control unit, which supplies a “stiff DC source” to the DC-AC converter. The seamless mode change is implemented in the DC-AC converter control module via three digital switches between power flow control for grid-connected mode (or MPPT mode), and droop control for islanded mode (or droop mode), while preserving the continuity of control signals in all control units with the configurations of digital switches.

Abstract: A utility management system and method including a water collection apparatus; a water storage apparatus in fluid communication with the water collection apparatus; a water storage quantity sensor; one or more water usage sensors; an energy generation apparatus; an energy storage apparatus coupled to the energy generation apparatus; an energy storage quantity sensor; one or more energy usage sensors; a processor with one or more channels to receive at least weather forecast data, water usage data, and energy usage data, and one or more channels to send at least a request for weather forecast data, wherein the processor is coupled to the one or more water usage sensors and energy usage sensors, and wherein the processor is programmed to use the received data to project water collection, water storage, energy generation, and energy storage and to formulate recommendations for water and energy usage; a control interface; and a data display.

Abstract: A control system and method include a control strategy and a UDE (Uncertainty and Disturbance Estimator)-based controller incorporated into the control strategy to achieve proportional load sharing for parallel-operated inverters. The UDE-based controller regulates the reactive power against the output generated by a reactive power reference unit according to the load voltage to generate the amplitude of the control voltage. The conventional droop method regulates real power to generate the phase of the control voltage. As a result, the model uncertainties (e.g., parameter drifts and uncertain output impedance), and system disturbances (e.g., fluctuating DC-link voltage and load change) can be estimated and compensated for accurate load sharing.

Abstract: A control system and method include a control strategy and a UDE (Uncertainty and Disturbance Estimator)-based controller incorporated into the control strategy to achieve proportional load sharing for parallel-operated inverters. The UDE-based controller regulates the reactive power against the output generated by a reactive power reference unit according to the load voltage to generate the amplitude of the control voltage. The conventional droop method regulates real power to generate the phase of the control voltage. As a result, the model uncertainties (e.g., parameter drifts and uncertain output impedance), and system disturbances (e.g., fluctuating DC-link voltage and load change) can be estimated and compensated for accurate load sharing.

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract: A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Abstract: Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.